A dual-side cooling (DSC) semiconductor package includes a first metal-insulator-metal (MIM) substrate having a first insulator layer, first metallic layer, and second metallic layer. A second MIM substrate includes a second insulator layer, third metallic layer, and fourth metallic layer. The third metallic layer includes a first portion having a first contact area and a second portion, electrically isolated from the first portion, having a second contact area. A semiconductor die is coupled with the second metallic layer and is directly coupled with the third metallic layer through one or more solders, sintered layers, electrically conductive tapes, solderable top metal (STM) layers, and/or under bump metal (UBM) layers. The first contact area is electrically coupled with a first electrical contact of the die and the second contact area is electrically coupled with a second electrical contact of the die. The first and fourth metallic layers are exposed through an encapsulant.

A composite assembly of three stacked joining partners, and a corresponding method. The three stacked joining partners are materially bonded to one another by an upper solder layer and a lower solder layer. An upper joining partner and a lower joining partner are fixed in their height and have a specified distance from one another. The upper solder layer is fashioned from a first solder agent, having a first melt temperature, between the upper joining partner and a middle joining partner. The second solder layer is fashioned from a second solder agent, having a higher, second melt temperature, between the middle joining partner and the lower joining partner. The upper joining partner has an upwardly open solder compensating opening filled with the first solder agent, from which, to fill the gap between the upper joining partner and the middle joining partner, the first solder agent subsequently flows into the gap.

An electronic system is disclosed. In one example, the electronic system comprises an at least partially electrically conductive carrier, an electronic component, and an intermetallic connection structure connecting the carrier and the component. The intermetallic connection structure comprising an intermetallic mesh structure in a central portion of the intermetallic connection structure, and opposing exterior structures without intermetallic mesh and each arranged between the intermetallic mesh structure and the carrier or the component.

A semiconductor package including a base comprising an upper surface and a lower surface that is opposite to the upper surface; a radio-frequency (RF) module embedded near the upper surface of the base; an integrated circuit (IC) die mounted on the lower surface of the base in a flip-chip manner so that a backside of the IC die is available for heat dissipation; a plurality of conductive structures disposed on the lower surface of the base and arranged around the IC die; and a metal thermal interface layer comprising a backside metal layer that is in contact with the backside of the IC die, and a solder paste conformally printed on the backside metal layer.

A semiconductor package including a base comprising an upper surface and a lower surface that is opposite to the upper surface; a radio-frequency (RF) module embedded near the upper surface of the base; an integrated circuit (IC) die mounted on the lower surface of the base in a flip-chip manner so that a backside of the IC die is available for heat dissipation; a plurality of conductive structures disposed on the lower surface of the base and arranged around the IC die; and a metal thermal interface layer comprising a backside metal layer that is in contact with the backside of the IC die, and a solder paste conformally printed on the backside metal layer.

In one embodiment, methods for making semiconductor devices are disclosed.

In one embodiment, methods for making semiconductor devices are disclosed.

A semiconductor device includes: a substrate; a semiconductor element arranged on the substrate; a plate-like member electrically connected to the semiconductor element; a first electrode formed on the semiconductor element and joined to the plate-like member with solder; a second electrode formed on the semiconductor element and spaced from the first electrode, and including a metal capable of forming an alloy with the solder; and a metal film formed on the semiconductor element and spaced from the second electrode in a region on the first electrode side as seen from the second electrode, in a two-dimensional view of the semiconductor element as seen from the plate-like member, and including a metal capable of forming an alloy with the solder.

A semiconductor device includes: a substrate; a semiconductor element arranged on the substrate; a plate-like member electrically connected to the semiconductor element; a first electrode formed on the semiconductor element and joined to the plate-like member with solder; a second electrode formed on the semiconductor element and spaced from the first electrode, and including a metal capable of forming an alloy with the solder; and a metal film formed on the semiconductor element and spaced from the second electrode in a region on the first electrode side as seen from the second electrode, in a two-dimensional view of the semiconductor element as seen from the plate-like member, and including a metal capable of forming an alloy with the solder.

An electronic apparatus including a substrate, a plurality of first bonding pads, an electronic device, and a first spacer is provided. The first bonding pads are disposed on the substrate. The electronic device is disposed on the substrate and electrically connected to the first bonding pads. The first spacer is disposed between the electronic device and the substrate. The electronic device is capable of effectively controlling a height and uniformity of a gap between the electronic device and the substrate, so as to prevent the electronic device from being tilted and ensure the electronic device to have a favorable structural reliability.