A chip package structure can include: a lead frame having a carrier substrate and a first lead around the carrier substrate; a first conductive post arranged on the first lead and electrically coupled with the first lead; a first chip having an active face and an inactive face opposite to the active face and attached to the carrier substrate, and electrode pads on the active face are provided with a first electrical connector; a first plastic package configured to fully encapsulate the first chip, and to partly encapsulate the lead frame, where the first plastic package includes a first surface and a second surface opposite to the first surface, where the first conductive post and the first electrical connector are exposed on the first surface, and where the first lead is exposed on the second surface, and a second lead being arranged on the first surface.

A connector for coupling an electronic component having an external connector pad to another structure, comprising an anisotropic conductive elastomer or adhesive composite comprising a plurality of separate columns of conductive particles held in an insulating matrix, with a top particle exposed to a surface of the matrix, wherein at least the top particle is coated with a metal that can permanently bond to the connector pad of the electronic component. Also disclosed are a related method, and a related electronic assembly.

An anisotropic conductive film including an electrically insulating adhesive layer, and electrically conductive particles disposed on the electrically insulating adhesive layer. In such an anisotropic conductive film, the electrically conductive particles are disposed in a lattice by being arranged in first direction rows and second direction rows, and narrow and wide intervals are provided between neighboring rows in at least one of the direction rows. As a result, opposing terminals are stably connected using the anisotropic conductive film, inspection after the connecting is more easily performed, and the number of electrically conductive particles not involved in the connection are reduced and, thereby, the manufacturing cost of the anisotropic conductive film is reduced, even in FOG connections or the like with finer bump pitches.

Techniques for packaging an integrated circuit include attaching a die to a conductive layer before forming dielectric layers on an opposing surface of the conductive layer. The conductive layer may first be formed on a carrier substrate before the die is disposed on the conductive layer. The die may be electrically coupled to the conductive layer via wires or solder bumps. The carrier substrate is removed before the dielectric layers are formed. The dielectric layers may collectively form a coreless package substrate for the integrated circuit package.

A conductive composition, which can form bonded portions and is capable of maintaining a thickness of the bonded portions and bonding strength, and which includes: (A) silver fine particles having a number average particle diameter of primary particles of 40 nm to 400 nm, (B) a solvent, and (C) thermoplastic resin particles having a maximal value of an endothermic peak in a DSC chart, determined by a measurement using a differential scanning calorimeter, within a range of 80° C. to 170° C.

In a display device, in which an IC chip, which has an output and an input bump group, is mounted onto a display panel via an ACF, and a total area of end surfaces of output bumps that form the output bump group is larger than a total area of end surfaces of input bumps that form the input bump group, a concentration of conductive particles in a portion of the ACF corresponding to the output bump group is lower than a concentration of conductive particles in a portion of the ACF corresponding to the input bump group.

A multichip package and a method for manufacturing the same are provided. A multichip package includes: a plurality of semiconductor chips each mounted on corresponding lead frame pads; lead frames connected to the semiconductor chips by a bonding wire; and fixed frames integrally formed with at least one of the lead frame pads and configured to support the lead frame pads on a package-forming substrate.

A driver mounting apparatus 40 includes a driver mount-side heat supply support member 42, a substrate support member 41, a driver-side heat supply support member 43, a first moving portion 44, and a second moving portion 45. The driver mount-side heat supply support member 42 supports a driver mount portion GSd and supplies heat to the driver mount portion GSd. The substrate support member supports a substrate main portion GSm. The driver-side heat supply support member 43 supports and sandwich a driver 21 with the driver mount-side heat supply support member 42 and supplies heat to the driver 21. The first moving portion 44 relatively moves the driver mount portion GSd and the driver mount-side heat supply support member 42 in an overlapping direction in which the glass substrate GS and the driver 21 are overlapped. The second moving portion 45 relatively moves the driver 21 and the driver-side heat supply support member 43 in the overlapping direction.

An anisotropic conductive film with a structure wherein an electrically insulting adhesive base layer and cover layer are stacked, and electrically conductive particles are disposed at lattice points with a planar lattice pattern in the vicinity of the interface of the layers. In the anisotropic conductive film, a proportion of lattice points at which no electrically conductive particles are disposed with respect to all lattice points with the planar lattice pattern assumed in any reference region is 25% or less, and some of the electrically conductive particles disposed at lattice points with planar lattice pattern are disposed to be shifted in longitudinal direction of anisotropic conductive film with respect to corresponding lattice points, and a shift amount defined as a distance between a plane projection center of the electrically conductive particles disposed to be shifted and the corresponding lattice point is less than 50% the electrically conductive particles' average diameter.

The present invention provides a flow guiding structure of chip, which comprises at least one flow guiding member disposed on a surface of a chip and adjacent to a plurality of connecting bumps disposed on the surface of the chip. When the chip is disposed on a board member, the at least one flow guiding member may guide the conductive medium on the surface of the chip to flow toward the connecting bumps and drive a plurality of conductive particles of the conductive medium to move toward the connecting bumps and thus increasing the number of the conductive particles on the surfaces of the connecting bumps. Alternatively, the flow guiding member may retard the flow of the conductive medium for avoiding the conductive particles from leaving the surfaces of the connecting bumps and thus preventing reduction of the number of the conductive particles on the surfaces of the connecting bumps.