The present disclosure relates to a TFT array substrate and a display panel including the same. The TFT array substrate includes a first substrate and a circuit layer disposed on a side of the first substrate; wherein the circuit layer comprises a first electrode layer, an insulating layer, a first pad layer, and a planarization layer; the first electrode layer comprises a plurality of first electrodes disposed on the side of the first substrate, and the first electrodes are electrodes of thin film transistors in the TFT array substrate; the insulating layer is disposed on a side of the first electrode layer away from the first substrate; the first pad layer comprises a plurality of first pads disposed on a side of the insulating layer away from the first electrode layer; the plurality of first pads are electrically connected to the plurality of first electrodes through contact holes respectively penetrating the insulating layer; the planarization layer is disposed on the side of the insulating layer away from the first electrode layer; the insulating layer is provided with a plurality of trenches, and a projection of each of the trenches on the first substrate respectively covers a projection of a corresponding edge of the first pads on the first substrate.

A neural recording probe and interface, along with a method of assembly, with the neural recording probe being minimally invasive and having high-density, multi-channel microelectrodes. In one example, the neural probe includes a plurality of bumps projecting from a bottom surface of a terminal body. Each bump is electrically connected to a corresponding one of a plurality of electrodes. The plurality of bumps is bonded to a respective one of a plurality of area pads of the integrated circuit with an anisotropic conductive film such that each of the plurality of electrodes of the neural probe is electrically connected to a respective one of the active circuits of the integrated circuit.

A semiconductor package includes a substrate having a first surface and a second surface opposing the first surface; a plurality of first pads disposed on the first surface of the substrate and a plurality of second pads disposed on the second surface of the substrate and electrically connected to the plurality of first pads; a semiconductor chip disposed on the first surface of the substrate and connected to the plurality of first pads; a dummy chip having a side surface facing one side surface of the semiconductor chip, disposed on the first surface of the substrate spaced apart from the semiconductor chip in a direction parallel to the first surface of the substrate, the dummy chip having an upper surface positioned lower than an upper surface of the semiconductor chip in a direction perpendicular to the first surface of the substrate; an underfill disposed between the semiconductor chip and the first surface of the substrate, and having an extension portion extended along the facing side surfaces of the semiconductor chip and the dummy chip in the direction perpendicular to the first surface of the substrate, an upper end of the extension portion being disposed to be lower than the upper surface of the semiconductor chip; and a sealing material disposed on the first surface of the substrate, and sealing the semiconductor chip and the dummy chip.

A semiconductor package includes a substrate having a first surface and a second surface opposing the first surface; a plurality of first pads disposed on the first surface of the substrate and a plurality of second pads disposed on the second surface of the substrate and electrically connected to the plurality of first pads; a semiconductor chip disposed on the first surface of the substrate and connected to the plurality of first pads; a dummy chip having a side surface facing one side surface of the semiconductor chip, disposed on the first surface of the substrate spaced apart from the semiconductor chip in a direction parallel to the first surface of the substrate, the dummy chip having an upper surface positioned lower than an upper surface of the semiconductor chip in a direction perpendicular to the first surface of the substrate; an underfill disposed between the semiconductor chip and the first surface of the substrate, and having an extension portion extended along the facing side surfaces of the semiconductor chip and the dummy chip in the direction perpendicular to the first surface of the substrate, an upper end of the extension portion being disposed to be lower than the upper surface of the semiconductor chip; and a sealing material disposed on the first surface of the substrate, and sealing the semiconductor chip and the dummy chip.

A method of connecting a plurality of electronic components to a flexible circuit board comprises: providing a carrier substrate carrying the electronic components, each of the electronic components having at least one electrical contact coated with electrically conductive adhesive; and applying the carrier substrate to the flexible circuit board such that the electronic components are adhered to the flexible circuit board in electrical contact therewith via the conductive adhesive. The electronic components may comprise LEDs and there may be provided one or more optical layers over the flexible circuit board.

A display module includes: a substrate; a side wiring extending along a side surface of the substrate, the side wiring electrically connecting a TFT layer of the substrate at a first end of the side wiring with a rear wiring layer of the substrate at a second end of the side wiring; a front cover disposed on and bonded with a mounting surface of the substrate; a metal plate disposed on and bonded with the rear surface; a side cover covering the side wiring and the side surface; a waterproof member configured to seal the second end of the side wiring from outside and prevent moisture permeation; and a side end member disposed on and covering the side cover and the waterproof member, and the side end member being grounded to the metal plate.

This member connection method includes: a cutting step of forming cutting lines C in an adhesive layer at predetermined intervals at least in a width direction of an adhesive tape and making segments of the adhesive layer divided by the cutting lines C continuous at least in a lengthwise direction of the adhesive tape; a transfer step of disposing the segments to face a connection surface of one member to be connected, pressing a heating and pressing tool having an arbitrary pattern shape against the adhesive tape from a separator side and selectively transferring the segments to the one member to be connected; and a connection step for connecting another member to be connected to the one member to be connected via the segments transferred to the one member to be connected.

The purpose of the invention is to counter measure a disconnection between the driver IC and the terminal when the terminal area of the electronic device is curved. One of the structures is as follows. An electronic device comprising: a driver IC installed in a terminal area, the terminal area being curved, wherein the driver IC has a circuit and plural bumps, the driver IC has a tapered portion formed on an opposite surface from a surface that the plural bumps are formed, the tapered portion overlaps with an outer most bump of the plural bumps.

An integrated circuit packaging method and an integrated packaging circuit, the integrated circuit packaging method including: circuit layers are provided on the top surface of a substrate, the bottom surface of the substrate or the interior of the substrate, the circuit layers having circuit pins; the substrate is provided with connection through holes, and the connection through holes are joined up with the circuit pins; a device is placed on the substrate, and the device is provided with device pins on a surface facing the substrate, which makes the device pins join up with a first opening of the connection through holes; conductive layers are fabricated in the connection through holes by means of a second opening of the connection through holes; and the conductive layers electrically connect the device pins to the circuit pins.

Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate having a first surface and an opposing second surface, and a die secured to the package substrate, wherein the die has a first surface and an opposing second surface, the die has first conductive contacts at the first surface and second conductive contacts at the second surface, and the first conductive contacts are coupled to conductive pathways in the package substrate by first non-solder interconnects.