A light-emitting module includes a common carrier; a plurality of semiconductor devices formed on the common carrier, and each of the plurality of semiconductor devices including three semiconductor dies; a carrier including a connecting surface; a third bonding pad and a fourth bonding pad formed on the connecting surface; and a connecting layer. One of the three semiconductor dies includes a stacking structure; a first bonding pad; and a second bonding pad with a shortest distance less than 150 microns between the first bonding pad. The connecting layer includes a first conductive part including a first conductive material having a first shape; and a blocking part covering the first conductive part and including a second conductive material having a second shape with a diameter in a cross-sectional view. The first shape has a height greater than the diameter.

A semiconductor package includes a package substrate, a lower semiconductor chip on the package substrate, a heat emission member on the lower semiconductor chip, the heat emission member having a horizontal unit and a vertical unit connected to the horizontal unit, a first semiconductor chip stack and a second semiconductor chip stack on the horizontal unit, and a molding member that surrounds the lower semiconductor chip, the first and second semiconductor chip stacks, and the heat emission member. The vertical unit may be arranged between the first semiconductor chip stack and the second semiconductor chip stack, and an upper surface of the vertical unit may be exposed in the molding member.

A semiconductor package includes a package substrate, a lower semiconductor chip on the package substrate, a heat emission member on the lower semiconductor chip, the heat emission member having a horizontal unit and a vertical unit connected to the horizontal unit, a first semiconductor chip stack and a second semiconductor chip stack on the horizontal unit, and a molding member that surrounds the lower semiconductor chip, the first and second semiconductor chip stacks, and the heat emission member. The vertical unit may be arranged between the first semiconductor chip stack and the second semiconductor chip stack, and an upper surface of the vertical unit may be exposed in the molding member.

An electro-optic assembly includes a layer of electro-optic material configured to switch optical states upon application of an electric field and an anisotropically conductive layer having one or more moisture-resistive polymers and a conductive material, the moisture-resistive polymer having a WVTR less than 5 g/(m.sup.2*d).

An inventive composition and process for formation of a conductive bonding film are disclosed. The invention combines adhesive bonding sheet technologies (e.g. die attach films, or DAFs) with the electrical and thermal conductivity performance of transient liquid phase sintered paste compositions. The invention films are characterized by high bulk thermal and electrical conductivity within the film as well as low and stable thermal and electrical resistance at the interfaces between the inventive film and metallized adherends.

An inventive composition and process for formation of a conductive bonding film are disclosed. The invention combines adhesive bonding sheet technologies (e.g. die attach films, or DAFs) with the electrical and thermal conductivity performance of transient liquid phase sintered paste compositions. The invention films are characterized by high bulk thermal and electrical conductivity within the film as well as low and stable thermal and electrical resistance at the interfaces between the inventive film and metallized adherends.

A semiconductor structure is disclosed. The semiconductor structure includes: a polymer base layer; a backside redistribution layer (RDL) over the polymer base layer; a molding layer over the backside RDL; a polymer layer over the molding layer; a front side RDL over the polymer layer; and a metal-insulator-metal (MIM) capacitor vertically passing through the molding layer, the MIM capacitor including a first electrode, an insulation layer and a second electrode, wherein the insulation layer surrounds the first electrode, and the second electrode surrounds the insulation layer, and the molding layer surrounds the second electrode. An associated method for manufacturing a semiconductor structure is also disclosed.

An applying method includes the following steps. Firstly, a conductive adhesive including a plurality of conductive particles and an insulating binder is provided. Then, a carrier plate is provided. Then, a patterned adhesive is formed on the carrier plate by the conductive adhesive, wherein the patterned adhesive includes a first transferring portion. Then, a manufacturing device including a needle is provided. Then, the needle of the manufacturing device is moved to contact the first transferring portion. Then, the transferring portion is transferred to a board by the manufacturing device.

An applying method includes the following steps. Firstly, a conductive adhesive including a plurality of conductive particles and an insulating binder is provided. Then, a carrier plate is provided. Then, a patterned adhesive is formed on the carrier plate by the conductive adhesive, wherein the patterned adhesive includes a first transferring portion. Then, a manufacturing device including a needle is provided. Then, the needle of the manufacturing device is moved to contact the first transferring portion. Then, the transferring portion is transferred to a board by the manufacturing device.

A method of manufacturing a semiconductor device includes a step of preparing a semiconductor element including a functional surface on which a bump is formed and an adhesive layer of a film shape including a flux component, a step of positioning the semiconductor element above a board including an electrode, a step of activating a flux component by applying ultrasonic vibration to the semiconductor element, a step of bringing the bump into contact with the electrode by pressing the semiconductor element to the board, and a step of bonding the bump to the electrode by continuing the application of the ultrasonic vibration and the pressing of the semiconductor element.