The present disclosure describes a method to form a bonded semiconductor structure. The method includes forming a first bonding layer on a first wafer, forming a debonding structure on a second wafer, forming a second bonding layer on the debonding structure, bonding the first and second wafers with the first and second bonding layers, and debonding the second wafer from the first wafer via the debonding structure. The debonding structure includes a first barrier layer, a second barrier layer, and a water-containing dielectric layer between the first and second barrier layers.

A semiconductor package structure and a method of manufacturing the same are provided. The semiconductor package structure includes an electronic component having a first surface, a second surface opposite to the first surface and a circuit structure closer to the first surface than to the second surface. The semiconductor package structure also includes a passive component connected to the second surface of the electronic component. The semiconductor package structure further includes a conductive element extending into the electronic component and configured to electrically connect the circuit structure with the passive component.

In one embodiment, a semiconductor wafer includes a first substrate, a first insulator provided on the first substrate, and a plurality of first pads provided in the first insulator. The wafer further includes a second insulator provided on the first insulator, a plurality of second pads provided on the first pads in the second insulator, a stacked film alternately including a plurality of first insulating layers and a plurality of second insulating layers provided in the second insulator, and a second substrate provided on the second insulator. Furthermore, the first insulator and the second insulator are connected to each other between an edge face of the first insulator and an edge face of the second insulator, and the second insulator intervenes between the first insulator and the stacked film at the edge faces of the first and second insulators.

A microelectronic device comprises a first control logic region comprising first control logic devices and a memory array region vertically overlying the first control logic region. The memory array region comprises capacitors, access devices laterally neighboring and in electrical communication with the capacitors, conductive lines operatively associated with the access devices and extending in a lateral direction, and first conductive pillars operatively associated with the access devices and vertically extending through the memory array region. The microelectronic device further comprises a second control logic region comprising second control logic devices vertically overlying the memory array region. Related microelectronic devices, memory devices, electronic systems, and methods are also described.

A microelectronic device comprises a first control logic region comprising first control logic devices and a memory array region vertically overlying the first control logic region. The memory array region comprises capacitors, access devices laterally neighboring and in electrical communication with the capacitors, conductive lines operatively associated with the access devices and extending in a lateral direction, and first conductive pillars operatively associated with the access devices and vertically extending through the memory array region. The microelectronic device further comprises a second control logic region comprising second control logic devices vertically overlying the memory array region. Related microelectronic devices, memory devices, electronic systems, and methods are also described.

A method includes forming a plurality of dielectric layers, forming a plurality of redistribution lines in the plurality of dielectric layers, forming stacked vias in the plurality of dielectric layers with the stacked vias forming a continuous electrical connection penetrating through the plurality of dielectric layers, forming a dielectric layer over the stacked vias and the plurality of dielectric layers, forming a plurality of bond pads in the dielectric layer, and bonding a device die to the dielectric layer and a first portion of the plurality of bond pads through hybrid bonding.

Three-dimensional (3D) memory devices and methods for forming the same are disclosed. In certain aspects, a 3D memory device includes a first semiconductor structure, a second semiconductor structure opposite to the first semiconductor structure, and an interface layer between the first semiconductor structure and the second semiconductor structure. The first semiconductor structure includes a memory stack having a plurality of interleaved stack conductive layers and stack dielectric layers. The second semiconductor structure includes a plurality of peripheral circuits electrically connected to the memory stack. The interface layer includes single crystalline silicon and a plurality of interconnects between the memory stack and the peripheral circuits.

An embodiment is a method including forming a first interconnect structure over a first substrate, the first interconnect structure comprising dielectric layers and metallization patterns therein, patterning the first interconnect structure to form a first opening, coating the first opening with a barrier layer, etching a second opening through the barrier layer and the exposed portion of the first substrate, depositing a liner in the first opening and the second opening, filling the first opening and the second opening with a conductive material, and thinning the first substrate to expose a portion of the conductive material in the second opening, the conductive material extending through the first interconnect structure and the first substrate forming a through substrate via.

A direct bond hybridization (DBH) method is provided. The DBH method includes preparing a first underlying layer, a first contact layer disposed on the first underlying layer and a first contact electrically communicative with the first underlying layer and protruding through the first contact layer, preparing a second underlying layer, a second contact electrically communicative with the second underlying layer and formed of softer material than the first contact and a second contact layer disposed on the second underlying layer and defining an aperture about the second contact and a moat at least partially surrounding the second contact and bonding the first and second contact layers whereby the first contact contacts the second contact such that the second contact deforms and expands into the moat.

A method for manufacturing a semiconductor device is provided. The method includes a step of performing a chemical mechanical polishing process on a first silicon oxide layer to form a planar surface layer; surface treatment is performed on the planar surface layer to form a treated planarization layer, and a second silicon oxide layer is formed on the treated planarization layer.