A bonding structure is provided, wherein the bonding structure includes a first substrate, a second substrate, a first adhesive layer, a second adhesive layer, and a silver feature. The second substrate is disposed opposite to the first substrate. The first adhesive layer is disposed on the first substrate. The second adhesive layer is disposed on the second substrate and opposite the first adhesive layer. The silver feature is disposed between the first adhesive layer and the second adhesive layer. The silver feature includes a silver nano-twinned structure that includes twin boundaries that are arranged in parallel. The parallel-arranged twin boundaries include 90% or more [111] crystal orientation.

A bonding structure is provided, wherein the bonding structure includes a first substrate, a second substrate, a first adhesive layer, a second adhesive layer, and a silver feature. The second substrate is disposed opposite to the first substrate. The first adhesive layer is disposed on the first substrate. The second adhesive layer is disposed on the second substrate and opposite the first adhesive layer. The silver feature is disposed between the first adhesive layer and the second adhesive layer. The silver feature includes a silver nano-twinned structure that includes twin boundaries that are arranged in parallel. The parallel-arranged twin boundaries include 90% or more [111] crystal orientation.

Atomic diffusion bonding is carried out using a bonding film comprising a nitride formed at a bonding surface. Operating in a vacuum chamber, a bonding film comprising a nitride is formed on each of flat surfaces of two substrates that each have the flat surface, and, by overlapping the two substrates so the bonding films formed on the two substrates are in contact with each other, the two substrates are joined by the generation of atomic diffusion at a bonding interface between the bonding films.

Embodiments of three-dimensional (3D) memory devices with a 3D NAND memory array having a plurality of pages, an on-die cache coupled to the memory array on a same chip and configured to cache a plurality of batches of program data between a host and the memory array, the on-die cache having SRAM cells, and a controller coupled to the on-die cache on the same chip. The controller is configured to check a status of an (N−2).sup.th batch of program data, N being an integer equal to or greater than 2, program an (N−1).sup.th batch of program data into respective pages in the 3D NAND memory array, and cache an N.sup.th batch of program data in respective space in the on-die cache as a backup copy of the N.sup.th batch of program data.

A hybrid silicon carbide (SiC) device includes a first device structure having a first substrate comprising SiC of a first conductivity type and a first SiC layer of the first conductivity type, where the first SiC layer is formed on a face of the first substrate. The first device structure also includes a second SiC layer of a second conductivity type that is formed on a face of the first SiC layer and a first contact region of the first conductivity type, where the first contact region traverses the second SiC layer and contacts the first SiC. The device also includes a second device structure that is bonded to the first device structure. The second device structure includes a switching device formed on a second substrate and a second contact region that traverses a first terminal region of the switching device and contacts the first contact region.

A memory device is provided. The memory device includes: a cell region including a first metal pad, a memory cell in the cell region configured to store weight data, a peripheral region including a second metal pad and vertically connected to the memory cell by the first metal pad and the second metal pad, a buffer memory in the peripheral region configured to read the weight data from the memory cell, an input/output pad in the peripheral region configured to receive input data; and a multiply-accumulate (MAC) operator in the peripheral region configured to receive the weight data from the buffer memory and receive the input data from the input/output pad to perform a convolution operation of the weight data and the input data, wherein the input data is provided to the MAC operator during a first period, and wherein the MAC operator performs the convolution operation of the weight data and the input data during a second period overlapping with the first period.

A method of manufacturing a semiconductor device includes forming a cell chip including a first substrate, a source layer on the first substrate, a stacked structure on the source layer, and a channel layer passing through the stacked structure and coupled to the source layer, flipping the cell chip, exposing a rear surface of the source layer by removing the first substrate from the cell chip, performing surface treatment on the rear surface of the source layer to reduce a resistance of the source layer, forming a peripheral circuit chip including a second substrate and a circuit on the second substrate, and bonding the cell chip including the source layer with a reduced resistance to the peripheral circuit chip.

A semiconductor structure and a forming method thereof are provided. One form of a semiconductor structure includes: a first device structure, including a first substrate and a first device formed on the first substrate, the first device including a first channel layer structure located on the first substrate, a first device gate structure extending across the first channel layer structure, and a first source-drain doping region located in the first channel layer structure on two sides of the first device gate structure; and a second device structure, located on a front surface of the first device structure, including a second substrate located on the first device structure and a second device formed on the second substrate, the second device including a second channel layer structure located on the second substrate, a second device gate structure extending across the second channel layer structure, and a second source-drain doping region located in the second channel layer structure on two sides of the second device gate structure, where projections of the second channel layer structure and the first channel layer structure onto the first substrate intersect non-orthogonally. The electricity of the first device can be led out according to the present disclosure.

Embodiments of semiconductor devices and fabrication methods thereof are disclosed. In an example, first semiconductor structures are formed. At least one of the first semiconductor structures includes a processor, static random-access memory (SRAM) cells, and a first bonding layer comprising first bonding contacts. Second semiconductor structures are formed. At least one of the second semiconductor structures comprises dynamic random-access memory (DRAM) cells and a second bonding layer comprising second bonding contacts. The first semiconductor structures and the second semiconductor structures are bonded. The first bonding contacts of the first semiconductor structure are in contact with the second bonding contacts of the second semiconductor structure. At least one of the first semiconductor structures and the second semiconductor structures further includes a peripheral circuit.

In an embodiment, a device includes: a bottom integrated circuit die having a first front side and a first back side; a top integrated circuit die having a second front side and a second back side, the second back side being bonded to the first front side, the top integrated circuit die being free from through substrate vias (TSVs); a dielectric layer surrounding the top integrated circuit die, the dielectric layer being disposed on the first front side, the dielectric layer and the bottom integrated circuit die being laterally coterminous; and a through via extending through the dielectric layer, the through via being electrically coupled to the bottom integrated circuit die, surfaces of the through via, the dielectric layer, and the top integrated circuit die being planar.