A solid top terminal for discrete power devices. In one embodiment, an apparatus is formed that includes a first die comprising a transistor, which in turn includes a first electrode such as an emitter. The apparatus also includes a first conductor sintered to an electroplated second conductor such as a solid top terminal. Importantly, the first conductor is electrically coupled to the first electrode.

A solid top terminal for discrete power devices. In one embodiment, an apparatus is formed that includes a first die comprising a transistor, which in turn includes a first electrode such as an emitter. The apparatus also includes a first conductor sintered to an electroplated second conductor such as a solid top terminal. Importantly, the first conductor is electrically coupled to the first electrode.

A contact region for a semiconductor substrate is disclosed. Embodiments can include forming a seed metal layer having an exposed solder pad region on the semiconductor substrate and forming a first metal layer on the seed metal layer. In an embodiment, a solderable material, such as silver, can be formed on the exposed solder pad region prior to forming the first metal layer. Embodiments can include forming a solderable material on the exposed solder pad region after forming the first metal layer. Embodiments can also include forming a plating contact region on the seed metal layer, where the plating contact region allows for electrical conduction during a plating process.

A performance of a semiconductor device is improved. The semiconductor device according to one embodiment includes a wire bonded to one bonding surface at a plurality of parts in an opening formed in an insulating film of a semiconductor chip. The semiconductor device includes also a sealer that seals the semiconductor chip and the wire so that the sealer is in contact with the bonding surface. The bonding surface includes a first region to which a bonding portion of the wire is bonded, a second region to which another bonding portion of the wire is bonded, and a third region between the first region and the second region. A width of the third region is smaller than a width of the first region and a width of the second region.

Provided is a semiconductor device with high reliability. In order to solve the above problems, according to the present invention, the semiconductor device includes a heat dissipating substrate, an insulating substrate arranged on the heat dissipating substrate and having a wiring layer, a plurality of semiconductor elements arranged on the insulating substrate, a conductive block electrically connected to a front surface electrode of the semiconductor element, and a terminal electrode, in which the conductive block has a convex portion, and the convex portion is bonded to the insulating substrate.

A method of die and clip attachment includes providing a clip, a die and a substrate, laminating a sinterable silver film on the clip and the die, depositing a tack agent on the substrate, placing the die on the substrate, placing the clip on the die and the substrate to create a substrate, die and clip package, lead and sintering the substrate, die and clip package.

A method of die and clip attachment includes providing a clip, a die and a substrate, laminating a sinterable silver film on the clip and the die, depositing a tack agent on the substrate, placing the die on the substrate, placing the clip on the die and the substrate to create a substrate, die and clip package, lead and sintering the substrate, die and clip package.

A bonding structure and a method for bonding components, wherein the bonding structure includes a nanoparticle preform. In accordance with embodiments, the nanoparticle preform is placed on a substrate and a workpiece is placed on the nanoparticle preform.

A stacked-chip assembly including a plurality of IC chips or die that are stacked, and a plurality of stacked leads. Leads from separate leadframes may be bonded together so as to tie corresponding metal features of the various chips to a same ground, signal, or power rail. Each leadframe may include a center paddle, which is disposed between two chips in the stack. The center paddle may function as one or more of a thermal conduit and common electrical rail (e.g., ground). The leadframes may be employed without the use of any bond wires with leads bonded directly to bond pads of the chips. A first IC chip may be mounted to a base leadframe and subsequent die-attach leadframes and IC chips are stacked upon the first IC chip and base leadframe. The die-attach leadframes may be iteratively bonded to an underlying leadframe and the bonded stacked leads stamped out of their respective leadframe sheets.

A stacked-chip assembly including a plurality of IC chips or die that are stacked, and a plurality of stacked leads. Leads from separate leadframes may be bonded together so as to tie corresponding metal features of the various chips to a same ground, signal, or power rail. Each leadframe may include a center paddle, which is disposed between two chips in the stack. The center paddle may function as one or more of a thermal conduit and common electrical rail (e.g., ground). The leadframes may be employed without the use of any bond wires with leads bonded directly to bond pads of the chips. A first IC chip may be mounted to a base leadframe and subsequent die-attach leadframes and IC chips are stacked upon the first IC chip and base leadframe. The die-attach leadframes may be iteratively bonded to an underlying leadframe and the bonded stacked leads stamped out of their respective leadframe sheets.