Packaging solutions for devices and systems comprising lateral GaN power transistors are disclosed, including components of a packaging assembly, a semiconductor device structure, and a method of fabrication thereof. In the packaging assembly, a GaN die, comprising one or more lateral GaN power transistors, is sandwiched between first and second leadframe layers, and interconnected using low inductance interconnections, without wirebonding. For thermal dissipation, the dual leadframe package assembly can be configured for either front-side or back-side cooling. Preferred embodiments facilitate alignment and registration of high current/low inductance interconnects for lateral GaN devices, in which contact areas or pads for source, drain and gate contacts are provided on the front-side of the GaN die. By eliminating wirebonding, and using low inductance interconnections with high electrical and thermal conductivity, PQFN technology can be adapted for packaging GaN die comprising one or more lateral GaN power transistors.

A second lead frame is set onto a conductive layer and a busbar. The second lead frame has holes previously formed at opposite ends thereof, and pieces of solder material or solder pieces are inserted into the holes. Then, the solder pieces are vibrated by an ultrasonically vibrating tool, whereby the solder pieces are melted without having a high temperature. The second lead frame is thus bonded to the conductive layer and the busbar. A semiconductor element and the busbar are connected by a first lead frame and the second lead frame. The connection structure thereof is such that the second lead frame to be bonded by ultrasonic bonding or other bonding methods is not directly in contact with the semiconductor element, which eliminates the risk of damage to the semiconductor element.

A second lead frame is set onto a conductive layer and a busbar. The second lead frame has holes previously formed at opposite ends thereof, and pieces of solder material or solder pieces are inserted into the holes. Then, the solder pieces are vibrated by an ultrasonically vibrating tool, whereby the solder pieces are melted without having a high temperature. The second lead frame is thus bonded to the conductive layer and the busbar. A semiconductor element and the busbar are connected by a first lead frame and the second lead frame. The connection structure thereof is such that the second lead frame to be bonded by ultrasonic bonding or other bonding methods is not directly in contact with the semiconductor element, which eliminates the risk of damage to the semiconductor element.

An object is to provide a semiconductor device in which heat generated in a lead electrode when conducting a large current can be reduced and the bonding quality between the lead electrode and a semiconductor element can be inspected easily. A semiconductor device includes: a base portion; a semiconductor element mounted on the base portion; a metal part erect with respect to the semiconductor element and having one end bonded, with a bonding material, to a principal surface of the semiconductor element opposite to another principal surface of the semiconductor element mounted on the base portion; and a lead electrode connected to the semiconductor element through the metal part. The lead electrode includes a through hole extending in a thickness direction. The metal part connects the semiconductor element to the lead electrode, while inserted into the through hole of the lead electrode together with a part of the bonding material.

An object is to provide a semiconductor device in which heat generated in a lead electrode when conducting a large current can be reduced and the bonding quality between the lead electrode and a semiconductor element can be inspected easily. A semiconductor device includes: a base portion; a semiconductor element mounted on the base portion; a metal part erect with respect to the semiconductor element and having one end bonded, with a bonding material, to a principal surface of the semiconductor element opposite to another principal surface of the semiconductor element mounted on the base portion; and a lead electrode connected to the semiconductor element through the metal part. The lead electrode includes a through hole extending in a thickness direction. The metal part connects the semiconductor element to the lead electrode, while inserted into the through hole of the lead electrode together with a part of the bonding material.

Disclosed is a temporary protective film for semiconductor sealing molding comprising: a support film; and an adhesive layer provided on one surface or both surfaces of the support film and containing a resin and a silane coupling agent, and the content of the silane coupling agent in the temporary protective film may be more than 5% by mass and less than or equal to 35% by mass with respect to the total mass of the resin.

Disclosed is a temporary protective film for semiconductor sealing molding comprising: a support film; and an adhesive layer provided on one surface or both surfaces of the support film and containing a resin and a silane coupling agent, and the content of the silane coupling agent in the temporary protective film may be more than 5% by mass and less than or equal to 35% by mass with respect to the total mass of the resin.

A semiconductor device includes a semiconductor die attached to a substrate and a metal clip attached to a side of the semiconductor die facing away from the substrate by a soldered joint. The metal clip has a plurality of slots dimensioned so as to take up at least 10% of a solder paste reflowed to form the soldered joint. Corresponding methods of production are also described.

A semiconductor device includes an insulating substrate formed by integrating a ceramic base plate and a cooling fin; a multiple of plate interconnection members; and a plurality of semiconductor elements. The one faces of the semiconductor elements are bonded to the ceramic base plate of the insulating substrate with a chip-bottom solder, and the other faces thereof are bonded to the plate-interconnection members with a chip-top solder so that plate interconnection members correspond respectively to the semiconductor elements. The chip-bottom solder and the chip-top solder both contain mainly Sn and 0.3-3 wt. % Ag and 0.5-1 wt. % Cu. This allows the semiconductor device to be reduced in size without impairing heat dissipation.

A semiconductor device includes an insulating substrate formed by integrating a ceramic base plate and a cooling fin; a multiple of plate interconnection members; and a plurality of semiconductor elements. The one faces of the semiconductor elements are bonded to the ceramic base plate of the insulating substrate with a chip-bottom solder, and the other faces thereof are bonded to the plate-interconnection members with a chip-top solder so that plate interconnection members correspond respectively to the semiconductor elements. The chip-bottom solder and the chip-top solder both contain mainly Sn and 0.3-3 wt. % Ag and 0.5-1 wt. % Cu. This allows the semiconductor device to be reduced in size without impairing heat dissipation.