Patent classifications
H01L2224/85013
Method for manufacturing a semiconductor device
After a die bonding step, a wire bonding step is performed to electrically connect the plurality of pad electrodes and the plurality of leads of the semiconductor chip via a plurality of copper wires. A plating layer is formed on a surface of the lead, and a copper wire is connected to the plating layer in the wire bonding step. The plating layer is a silver plating layer. After the die bonding step, an oxygen plasma treatment is performed on the lead frame and the semiconductor chip before the wire bonding step, and then the surface of the plating layer is reduced.
Semiconductor device and method of manufacturing thereof
The reliability of semiconductor device is improved. The method of manufacturing a semiconductor device has a step of performing plasma treatment prior to the wire bonding step, and the surface roughness of the pads after the plasma treatment step is equal to or less than 3.3 nm.
INTEGRATED CIRCUIT PACKAGING
An integrated circuit and methods for packaging the integrated circuit. In one example, a method for packaging an integrated circuit includes connecting input/output pads of a first integrated circuit die to terminals of a lead frame via palladium coated copper wires. An oxygen plasma is applied to the first integrated circuit die and the palladium coated copper wires. The first integrated circuit die and the palladium coated copper wires are encapsulated in a mold compound after application of the oxygen plasma.
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THEREOF
The reliability of semiconductor device is improved. The method of manufacturing a semiconductor device has a step of performing plasma treatment prior to the wire bonding step, and the surface roughness of the pads after the plasma treatment step is equal to or less than 3.3 nm.
Protection from ESD during the manufacturing process of semiconductor chips
According to principles of the disclosure as explained herein, selected leads are electrically connected through metal strips to the lead frame until the end of the manufacturing process. The lead frame is grounded through the manufacturing process to prevent any ESD event from causing damage to the protected leads. In the final singulation step, the leads are electrically isolated from each other and from the lead frame, thus maintaining protection from a potential ESD event up until the final package singulation step.
METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE
After a die bonding step, a wire bonding step is performed to electrically connect the plurality of pad electrodes and the plurality of leads of the semiconductor chip via a plurality of copper wires. A plating layer is formed on a surface of the lead, and a copper wire is connected to the plating layer in the wire bonding step. The plating layer is a silver plating layer. After the die bonding step, an oxygen plasma treatment is performed on the lead frame and the semiconductor chip before the wire bonding step, and then the surface of the plating layer is reduced.
Integrated circuit packaging
An integrated circuit package and methods for packaging an integrated circuit. In one example, a method for packaging an integrated circuit includes connecting input/output pads of a first die to terminals of a lead frame via palladium coated copper wires. An oxygen plasma is applied to the first die and the palladium coated copper wires. The first die and the palladium coated copper wires are encapsulated in a mold compound after application of the oxygen plasma.
Laminate stacked on die for high voltage isolation capacitor
An isolator device includes a laminate die having a dielectric laminate material with a metal laminate layer on one side of the dielectric laminate material, the metal laminate layer being a patterned layer providing at least a first plate, including a dielectric layer over the first plate that includes an aperture exposing a portion of the first plate. An integrated circuit (IC) including a substrate having a semiconductor surface includes circuitry including a transmitter and/or a receiver, the IC including a top metal layer providing at least a second plate coupled to a node in the circuitry, with at least one passivation layer on the top metal layer. A non-conductive die attach (NCDA) material for attaching a side of the dielectric laminate material is opposite the metal laminate layer to the IC so that the first plate is at least partially over the second plate to provide a capacitor.
PROTECTION FROM ESD DURING THE MANUFACTURING PROCESS OF SEMICONDUCTOR CHIPS
According to principles of the disclosure as explained herein, selected leads are electrically connected through metal strips to the lead frame until the end of the manufacturing process. The lead frame is grounded through the manufacturing process to prevent any ESD event from causing damage to the protected leads. In the final singulation step, the leads are electrically isolated from each other and from the lead frame, thus maintaining protection from a potential ESD event up until the final package singulation step.
Protection from ESD during the manufacturing process of semiconductor chips
According to principles of the disclosure as explained herein, selected leads are electrically connected through metal strips to the lead frame until the end of the manufacturing process. The lead frame is grounded through the manufacturing process to prevent any ESD event from causing damage to the protected leads. In the final singulation step, the leads are electrically isolated from each other and from the lead frame, thus maintaining protection from a potential ESD event up until the final package singulation step.