There is provided a novel Cu bonding wire that achieves a favorable FAB shape and achieves a favorable bond reliability of the 2nd bonded part even in a rigorous high-temperature environment. The bonding wire for semiconductor devices is characterized in that the bonding wire includes: a core material of Cu or Cu alloy; and a coating layer containing conductive metal other than Cu formed on a surface of the core material, wherein the coating layer has a region containing Pd as a main component on a core material side, and has a region containing Ni and Pd in a range from a wire surface to a depth of 0.5 d when a thickness of the coating layer is defined as d (nm) in a thickness direction of the coating layer, the thickness d of the coating layer is 10 nm or more and 130 nm or less, a ratio C.sub.Ni/C.sub.Pd of a concentration C.sub.Ni (mass %) of Ni to a concentration C.sub.Pd (mass %) of Pd relative to the entire wire is 0.02 or more and 0.7 or less, a position indicating a maximum concentration of Ni is present in the range from the wire surface to a depth of 0.5 d in a concentration profile in a depth direction of the wire, and the maximum concentration of Ni is 10 atomic % or more, and at least one of the following conditions (i) and (ii) is satisfied: (i) a concentration of In relative to the entire wire is 1 ppm by mass or more and 100 ppm by mass or less (ii) a concentration of Ag relative to the entire wire is 1 ppm by mass or more and 500 ppm by mass or less.

The bonding wire for semiconductor devices includes a core material of Cu or Cu alloy and a coating layer containing conductive metal other than Cu formed on a surface of the core material. The coating layer has a region containing Ni as a main component on a core material side, and has a region containing Au and Ni on a wire surface side, in a thickness direction of the coating layer, a thickness of the coating layer is 10 nm or more and 130 nm or less, a ratio of a concentration C.sub.Au (mass %) of Au to a concentration C.sub.Ni (mass %) of Ni relative to the entire wire is 0.02<C.sub.Au/C.sub.Ni?0.7, and a concentration of Au at the surface of the wire is 10 atomic % or more and 90 atomic % or less.

A method of forming a wire interconnect structure includes the steps of: (a) forming a wire bond at a bonding location on a substrate using a wire bonding tool; (b) extending a length of wire, continuous with the wire bond, to a position above the wire bond; (c) moving the wire bonding tool to contact the length of wire, at a position along the length of wire, to partially sever the length of wire at the position along the length of wire; and (d) separating the length of wire from a wire supply at the position along the length of wire, thereby providing a wire interconnect structure bonded to the bonding location.

A semiconductor device provided according to an aspect of the present disclosure includes a semiconductor element, a bonding target, a first wire, a wire strip and a second wire. The bonding target is electrically connected to the semiconductor element. The first wire is made of a first metal. The first wire includes a first bonding portion bonded to the bonding target and a first line portion extending from the first bonding portion. The wire strip is made of the first metal. The wire strip is bonded to the bonding target. The second wire is made of a second metal different from the first metal. The second wire includes a second bonding portion bonded to the bonding target via the wire strip and a second line portion extending from the second bonding portion.

To provide a novel Cu bonding wire that achieves a favorable FAB shape and a favorable bondability of the 2nd bonded part, and further achieves favorable bond reliability even in a rigorous high-temperature environment. The bonding wire for semiconductor devices includes: a core material of Cu or Cu alloy; and a coating layer containing conductive metal other than Cu formed on a surface of the core material, wherein the coating layer has a region containing Ni as a main component on a core material side, and has a region containing Au and Ni on a wire surface side, in a thickness direction of the coating layer, a thickness of the coating layer is 10 nm or more and 130 nm or less, a ratio C.sub.Au/C.sub.Ni of a concentration C.sub.Au (mass %) of Au to a concentration C.sub.Ni (mass %) of Ni relative to the entire wire is 0.02 or more and 0.7 or less, a concentration of Au at the surface of the wire is 10 atomic % or more and 90 atomic % or less, and at least one of the following conditions (i) and (ii) is satisfied: (i) a concentration of In relative to the entire wire is 1 ppm by mass or more and 100 ppm by mass or less (ii) a concentration of Ag relative to the entire wire is 1 ppm by mass or more and 500 ppm by mass or less.

Disclosed is a semiconductor device that includes a semiconductor chip; bonding pads provided to the semiconductor chip; a plurality of lead terminals arranged around the semiconductor chip; a plurality of bonding wires that electrically connect the semiconductor chip with the plurality of lead terminals; and a resin encapsulant which encapsulates the semiconductor chip and the bonding wires, the semiconductor device further having an insulating material interposed at the interface between the bonding wires and the resin encapsulant, and the insulating material containing a nanometer-sized insulating particle and amorphous silica.

A method for manufacturing a semiconductor device includes (i) a step of preparing a first semiconductor chip having a first electrode pad thereon and a second semiconductor chip having a second electrode pad thereon and larger in thickness than the first semiconductor chip, the second electrode pad being larger in size than the first electrode pad, (ii) a step of mounting the first semiconductor chip and the second semiconductor chip on the same planarized surface of a substrate having a uniform thickness, (iii) a step of bonding a ball formed by heating and melting a bonding wire to the second electrode pad, (iv) a step of first-bonding the bonding wire to the first electrode pad, and (v) a step of second-bonding the bonding wire to the ball.

A method of forming a wire interconnect structure includes the steps of: (a) forming a wire bond at a bonding location on a substrate using a wire bonding tool; (b) extending a length of wire, continuous with the wire bond, to a position above the wire bond; (c) moving the wire bonding tool to contact the length of wire, at a position along the length of wire, to partially sever the length of wire at the position along the length of wire; and (d) separating the length of wire from a wire supply at the position along the length of wire, thereby providing a wire interconnect structure bonded to the bonding location.

The present disclosure provides a wire bonding apparatus, a wire bonding method and a semiconductor device. The wire bonding apparatus includes: a wire tube for containing the wire and including a wire exit; a wire heating assembly located at a side of the wire exit; and a pre-shaping assembly located at a side of the wire tube and including a wire pre-pressing face; the pre-shaping assembly having a first state in which the wire pre-pressing face of the pre-shaping assembly is configured to abut the wire tube and a second state in which the pre-shaping assembly is configured to disengage from the wire tube. The wire bonding apparatus, the wire bonding method and the semiconductor device as provided in the present disclosure can reduce or eliminate the cratering effect.

A package structure includes a mounting pad having a mounting surface; a semiconductor chip having a magnetic device, a first magnetic field shielding, and a molding. The semiconductor chip comprises a first surface perpendicular to a thickness direction of the semiconductor chip, a second surface opposite to the first surface, wherein the second surface is attached to the mounting surface of the mounting pad, and a third surface connecting the first surface and the second surface. The first magnetic field shielding including a plurality of segments laterally at least partially surrounding the semiconductor chip, wherein a bottom surface of the first magnetic field shielding is attached to the mounting surface of the mounting pad, wherein the mounting surface comprises first portion free from overlapping with the first magnetic field shielding from a top view perspective. The molding surrounding the mounting pad and in direct contact with the mounting surface.