A method for manufacturing a semiconductor device includes forming a lead frame assembly in which a first side wall portion and a second side wall portion, both made of a resin, are joined to each other in a state of having a metal lead frame sandwiched therebetween; applying a sintering metal paste to a disposition region of the lead frame assembly and disposing the lead frame assembly on the sintering metal paste; and sintering the sintering metal paste between a metal base of the semiconductor device and the lead frame assembly to join the base and the lead frame assembly to each other.

A semiconductor package includes a metallic pad and leads spaced from the metallic pad by a gap, the metallic pad including a roughened surface. The semiconductor package further includes a semiconductor die including bond pads, and an adhesive between the roughened surface of the metallic pad and the semiconductor die, therein bonding the semiconductor die to the metallic pad, wherein the adhesive includes a resin. The metallic pad further includes a groove surrounding the semiconductor die on the roughened surface, the groove having a surface roughness less than a surface roughness of the roughened surface of the metallic pad.

A semiconductor package includes a metallic pad and leads spaced from the metallic pad by a gap, the metallic pad including a roughened surface. The semiconductor package further includes a semiconductor die including bond pads, and an adhesive between the roughened surface of the metallic pad and the semiconductor die, therein bonding the semiconductor die to the metallic pad, wherein the adhesive includes a resin. The metallic pad further includes a groove surrounding the semiconductor die on the roughened surface, the groove having a surface roughness less than a surface roughness of the roughened surface of the metallic pad.

A semiconductor package includes a metallic pad and leads spaced from the metallic pad by a gap, the metallic pad including a roughened surface. The semiconductor package further includes a semiconductor die including bond pads, and an adhesive between the roughened surface of the metallic pad and the semiconductor die, therein bonding the semiconductor die to the metallic pad, wherein the adhesive includes a resin. The metallic pad further includes a groove surrounding the semiconductor die on the roughened surface, the groove having a surface roughness less than a surface roughness of the roughened surface of the metallic pad.

A semiconductor package includes a metallic pad and leads spaced from the metallic pad by a gap, the metallic pad including a roughened surface. The semiconductor package further includes a semiconductor die including bond pads, and an adhesive between the roughened surface of the metallic pad and the semiconductor die, therein bonding the semiconductor die to the metallic pad, wherein the adhesive includes a resin. The metallic pad further includes a groove surrounding the semiconductor die on the roughened surface, the groove having a surface roughness less than a surface roughness of the roughened surface of the metallic pad.

It is an object to provide a Cu alloy bonding wire for a semiconductor device that can satisfy required performance in high-density LSI applications. In the Cu alloy bonding wire for a semiconductor device according to the present invention, each of abundance ratios of crystal orientations <100>, <110> and <111> having an angular difference of 15 degrees or less from a direction perpendicular to one plane including a wire center axis out of crystal orientations on a wire surface is 3% or more and less than 27% in average area percentage.

It is an object to provide a Cu alloy bonding wire for a semiconductor device that can satisfy required performance in high-density LSI applications. In the Cu alloy bonding wire for a semiconductor device according to the present invention, each of abundance ratios of crystal orientations <100>, <110> and <111> having an angular difference of 15 degrees or less from a direction perpendicular to one plane including a wire center axis out of crystal orientations on a wire surface is 3% or more and less than 27% in average area percentage.

It is an object to provide a Cu alloy bonding wire for a semiconductor device that can satisfy required performance in high-density LSI applications. In the Cu alloy bonding wire for a semiconductor device according to the present invention, each of abundance ratios of crystal orientations <100>, <110> and <111> having an angular difference of 15 degrees or less from a direction perpendicular to one plane including a wire center axis out of crystal orientations on a wire surface is 3% or more and less than 27% in average area percentage.

It is an object to provide a Cu alloy bonding wire for a semiconductor device that can satisfy required performance in high-density LSI applications. In the Cu alloy bonding wire for a semiconductor device according to the present invention, each of abundance ratios of crystal orientations <100>, <110> and <111> having an angular difference of 15 degrees or less from a direction perpendicular to one plane including a wire center axis out of crystal orientations on a wire surface is 3% or more and less than 27% in average area percentage.

A semiconductor device of an embodiment includes: a semiconductor substrate; a first insulating layer provided on or above the semiconductor substrate; an aluminum layer provided on the first insulating layer; a second insulating layer provided on the first insulating layer, the second insulating layer covering a first region of a surface of the aluminum layer; and an aluminum oxide film provided on a second region other than the first region of the surface of the aluminum layer, the aluminum oxide film including -alumina as a main component, and a film thickness of the aluminum oxide film being equal to or larger than 0.5 nm and equal to or smaller than 3 nm.