A leadless multichip semiconductor device includes a metal substrate having a through-hole aperture with an outer ring for holding a bottom semiconductor die with an inner row and an outer row of metal pads. The bottom semiconductor die has a back side metal (BSM) layer on its bottom side and a top side with bond pads mounted top side up on the ring. A metal die attach layer is directly between the BSM layer and walls of the metal substrate providing a die attachment that fills a bottom portion of the aperture. Bond wires are between the inner metal pads and the bond pads. A top semiconductor die has top bond pads mounted top side up on a dielectric adhesive on the bottom semiconductor die. Pins connect the top bond pads to the outer metal pads. A mold compound provides isolation between adjacent ones of the metal pads.

A leadless multichip semiconductor device includes a metal substrate having a through-hole aperture with an outer ring for holding a bottom semiconductor die with an inner row and an outer row of metal pads. The bottom semiconductor die has a back side metal (BSM) layer on its bottom side and a top side with bond pads mounted top side up on the ring. A metal die attach layer is directly between the BSM layer and walls of the metal substrate providing a die attachment that fills a bottom portion of the aperture. Bond wires are between the inner metal pads and the bond pads. A top semiconductor die has top bond pads mounted top side up on a dielectric adhesive on the bottom semiconductor die. Pins connect the top bond pads to the outer metal pads. A mold compound provides isolation between adjacent ones of the metal pads.

A leadless multichip semiconductor device includes a metal substrate having a through-hole aperture with an outer ring for holding a bottom semiconductor die with an inner row and an outer row of metal pads. The bottom semiconductor die has a back side metal (BSM) layer on its bottom side and a top side with bond pads mounted top side up on the ring. A metal die attach layer is directly between the BSM layer and walls of the metal substrate providing a die attachment that fills a bottom portion of the aperture. Bond wires are between the inner metal pads and the bond pads. A top semiconductor die has top bond pads mounted top side up on a dielectric adhesive on the bottom semiconductor die. Pins connect the top bond pads to the outer metal pads. A mold compound provides isolation between adjacent ones of the metal pads.

A sensor package structure and a sensing module thereof are provided. The sensor package structure includes a substrate, a sensor chip disposed on the substrate, a light-curing layer disposed on the sensor chip, a light-permeable layer arranged above the sensor chip through the light-curing layer, and a shielding layer disposed on a surface of the light-permeable layer. The light-curing layer has an inner lateral side and an outer lateral side opposite to the inner lateral side, and the inner lateral side is separated from the outer lateral side by a first distance. In a transverse direction parallel to a top surface of the sensor chip, the outer lateral side is separated from an outer lateral edge by a second distance which is within a range of to of the first distance.

A sensor package structure and a sensing module thereof are provided. The sensor package structure includes a substrate, a sensor chip disposed on the substrate, a light-curing layer disposed on the sensor chip, a light-permeable layer arranged above the sensor chip through the light-curing layer, and a shielding layer disposed on a surface of the light-permeable layer. The light-curing layer has an inner lateral side and an outer lateral side opposite to the inner lateral side, and the inner lateral side is separated from the outer lateral side by a first distance. In a transverse direction parallel to a top surface of the sensor chip, the outer lateral side is separated from an outer lateral edge by a second distance which is within a range of to of the first distance.

A multilayer composite bonding material with a plurality of thermal stress compensation layers is provided. The plurality of thermal stress compensation layers include a metal core layer, a pair of particle layers extending across the metal core layer such that the metal core layer is sandwiched between the pair of particle layers, and a pair of metal outer layers extending across the pair of particle layers such that the pair of particle layers are sandwiched between the pair of metal outer layers. A pair of low melting point (LMP) bonding layers extend across the pair of metal outer layers. The metal core layer, the pair of particle layers, and the pair of metal outer layers each have a melting point above a transient liquid phase (TLP) sintering temperature, and the pair of LMP bonding layers each have a melting point below the TLP sintering temperature.

A multilayer composite bonding material with a plurality of thermal stress compensation layers is provided. The plurality of thermal stress compensation layers include a metal core layer, a pair of particle layers extending across the metal core layer such that the metal core layer is sandwiched between the pair of particle layers, and a pair of metal outer layers extending across the pair of particle layers such that the pair of particle layers are sandwiched between the pair of metal outer layers. A pair of low melting point (LMP) bonding layers extend across the pair of metal outer layers. The metal core layer, the pair of particle layers, and the pair of metal outer layers each have a melting point above a transient liquid phase (TLP) sintering temperature, and the pair of LMP bonding layers each have a melting point below the TLP sintering temperature.

A power converting device such that an overcurrent is interrupted and damage to a power semiconductor element can be prevented is obtained. The power converting device includes a power semiconductor element, a wiring member connected to an electrode of the power semiconductor element, a bus bar that supplies power to the power semiconductor element, and a frame that houses the power semiconductor element, wherein the bus bar has a connection terminal connected to the wiring member, and a fuse portion is provided in the connection terminal.

A power converting device such that an overcurrent is interrupted and damage to a power semiconductor element can be prevented is obtained. The power converting device includes a power semiconductor element, a wiring member connected to an electrode of the power semiconductor element, a bus bar that supplies power to the power semiconductor element, and a frame that houses the power semiconductor element, wherein the bus bar has a connection terminal connected to the wiring member, and a fuse portion is provided in the connection terminal.

An image sensor chip-scale package includes a pixel array, a cover glass covering the pixel array, a dam, and an adhesive layer. The pixel array is embedded in a substrate top-surface of a semiconductor substrate. The semiconductor substrate includes a plurality of conductive pads in a peripheral region of the semiconductor substrate surrounding the pixel array. The dam at least partially surrounds the pixel array and is located (i) between the cover glass and the semiconductor substrate, and (ii) on a region of the substrate top-surface between the pixel array and the plurality of conductive pads. The adhesive layer is (i) located between the cover glass and the semiconductor substrate, (ii) at least partially surrounding the dam, and (iii) configured to adhere the cover glass to the semiconductor substrate.