A method for forming a semiconductor device package is provided. The method includes bonding a semiconductor device to a package substrate; placing a metal lid over the semiconductor device and the package substrate with a metal thermal interface material (TIM) provided between the metal lid and the semiconductor device; heating the metal TIM to melt the metal TIM; pressing the metal lid downward so that the molten metal TIM flows toward the boundary of the semiconductor device, and the outermost point of the lateral sidewall of the molten metal TIM extends beyond the boundary of the semiconductor device; lifting the metal lid upward so that the molten metal TIM flows back, and the outermost point of the lateral sidewall is within the boundary of the semiconductor device; and bonding the metal lid to the semiconductor device through the metal TIM by curing the molten metal TIM.

An integrated circuit package comprising one or more electronic component(s); a first substrate including a first surface and a second surface of the first substrate; and a second substrate including a first surface and a second surface of the second substrate. The first substrate including a first first-substrate cavity on the first surface of the first substrate. The second substrate includes a first second-substrate cavity on the first surface of the second substrate. The second surface of the first substrate and the second surface of the second substrate is located between the first surface of the first substrate and the first surface of the second substrate; or the first surface of the first substrate and the first surface of the second substrate is located between the second surface of the first substrate and the second surface of the second substrate.

In one example, a semiconductor device can comprise a substrate, a device stack, first and second internal interconnects, and an encapsulant. The substrate can comprise a first and second substrate sides opposite each other, a substrate outer sidewall between the first substrate side and the second substrate side, and a substrate inner sidewall defining a cavity between the first substrate side and the second substrate side. The device stack can be in the cavity and can comprise a first electronic device, and a second electronic device stacked on the first electronic device. The first internal interconnect can be coupled to the substrate and the device stack. The encapsulant can cover the substrate inner sidewall and the device stack and can fill the cavity. Other examples and related methods are disclosed herein.

There is provided an active phased array antenna in which power to an Si wafer is separated from power to compound semiconductor chips. An active phased array antenna is an active phased array antenna including a substrate having a plurality of antenna elements; a pseudo wafer containing a group of semiconductor chips including a plurality of semiconductor chips made of compound semiconductors; and a silicon wafer made of silicon, the substrate, the pseudo wafer, and the silicon wafer being stacked on top of each other in this order, and the pseudo wafer includes first feeders for supplying power to the group of semiconductor chips from the substrate; and a second feeder for supplying power to the silicon wafer from the substrate, the second feeder passing through the pseudo wafer in a thickness direction of the pseudo wafer.

Multiple (multi-) die integrated circuit (IC) packages for supporting higher connection density, and related fabrication methods. The multi-die IC package includes split dies that provided in respective die packages that are stacked on top of each other to conserve package area. To support signal routing, including through-package signal routing that extends through the die package, each die package includes vertical interconnects disposed adjacent to their respective dies and coupled to a respective package substrate (and interposer substrate if provided) in the package substrate. In this manner, as an example, through-silicon-vias (TSVs) are not required to be fabricated in the multi-die IC package that extend through the dies themselves to provide signal routing between the respective die packages. In another example, space created between adjacent interposer substrates of stacked die packages, as stood off from each other through the interconnect bumps, provides an area for heat dissipation.

A semiconductor device includes a first redistribution substrate, a semiconductor chip on a top surface of the first redistribution substrate, a conductive structure on the top surface of the first redistribution substrate and laterally spaced apart from the semiconductor chip, and a molding layer on the first redistribution substrate and covering a sidewall of the semiconductor chip and a sidewall of the conductive structure. The conductive structure includes a first conductive structure having a first sidewall, and a second conductive structure on a top surface of the first conductive structure and having a second sidewall. The first conductive structure has an undercut at a lower portion of the first sidewall. The second conductive structure has a protrusion at a lower portion of the second sidewall.

An interconnect for a semiconductor device includes a laminate substrate; a first plurality of electrical devices in or on a surface of the laminate substrate; a redistribution layer having a surface disposed on the surface of the laminate substrate; a second plurality of electrical devices in or on the surface of the redistribution layer; and a plurality of transmission lines between the first plurality of electrical devices and the second plurality of electrical devices. The surface of the laminate substrate and the surface of the redistribution layer are parallel to each other to form a dielectric structure and a conductor structure.

A semiconductor package is disclosed. The semiconductor package may include a first redistribution substrate including a first insulating layer and a first redistribution pattern, a lower semiconductor chip mounted on the first redistribution substrate, a conductive structure disposed on the first redistribution substrate and horizontally spaced apart from the lower semiconductor chip, a first mold layer interposed between the first redistribution substrate and the second redistribution substrate to cover the lower semiconductor chip and the conductive structure, a second redistribution substrate on the first redistribution substrate, the second redistribution substrate including a second insulating layer and a second redistribution pattern, a first heat-dissipation pattern interposed between the lower semiconductor chip and the second insulating layer, and a heat-dissipation pad on the conductive structure. A top surface of the first heat-dissipation pattern may be located at a level higher than a top surface of the conductive structure.

A semiconductor package includes: a first package substrate; a first semiconductor device mounted on the first package substrate; a second package substrate arranged on an upper part of the first semiconductor device; and a heat-dissipating material layer arranged between the first semiconductor device and the second package substrate and having a thermal conductivity of approximately 0.5 W/m.Math.K to approximately 20 W/m.Math.K, wherein the heat-dissipating material layer is in direct contact with an upper surface of the first semiconductor device and a conductor of the second package substrate.

A method includes forming a release film over a carrier, attaching a device over the release film through a die-attach film, encapsulating the device in an encapsulating material, performing a planarization on the encapsulating material to expose the device, detaching the device and the encapsulating material from the carrier, etching the die-attach film to expose a back surface of the device, and applying a thermal conductive material on the back surface of the device.