An optical sensor and filter assembly is provided and includes an optical sensor, a filter and a mounting structure. The optical sensor includes a detector layer having first and second opposed faces and a read-out integrated circuit (ROIC) to which the first face of the detector layer is hybridized. The filter permits passage of one or more wavelength bands of interest of incident light toward the optical sensor and the mounting structure directly hybridizes the filter to the second face of the detector layer.

A semiconductor device includes an insulation board, an electrode provided on the insulation board, a bonding layer provided on the electrode and made of a sintered body of metal particles having an average particle size of nano-order, and a semiconductor element bonded to the electrode via the bonding layer. A layer thickness of the bonding layer is greater than or equal to 220 μm and less than or equal to 700 μm.

In sonic examples, a method includes pre-stressing a flange, heating the flange to a die-attach temperature, and attaching a die to the flange at the die-attach temperature using a die-attach material. In some examples, the flange includes a metal material, the die-attach temperature may be at least two hundred degrees Celsius, and the die-attach material may include solder and/or an adhesive. In some examples, the method includes cooling the semiconductor die and metal flange to a room temperature after attaching the semiconductor die to the metal flange at the die-attach temperature using a die-attach material.

A power semiconductor module includes a semiconductor switching element, a gate control pattern to which a gate electrode of the semiconductor switching element is connected, a source control pattern to which a source electrode of the semiconductor switching element is connected, a capacitor to form a low-pass filter, a capacitor arrangement pattern to which one end of the capacitor is connected, and a wire. The other end of the capacitor is connected to the source control pattern. The wire electrically connects the capacitor arrangement pattern and the gate control pattern.

An object is to provide highly reliable semiconductor element bonding portion and semiconductor device that have high heat resistance and improved adhesion between a bonding material and a sealing resin. Provided is a semiconductor element bonding portion in which the semiconductor element 11 and an electrically conductive plate 123a are bonded to each other by a bonding layer 10 and the bonding layer 10 includes a metal nanoparticle sintered body 101 and a coupling agent 102 including an SH group.

A power conversion device includes a printed circuit board, whose mounting surface is opposite to an annular surface formed by an annular stator that constitutes a motor, arranged to be separated from the annular surface with a predetermined distance, and mounted with a Hall element that detects a rotation position of a rotor of the motor on a mounting surface on a side of the stator; an inverter IC that is mounted on the mounting surface on the side of the stator of the printed circuit board to supply a high-frequency current to the stator; and an overheat detection unit that is mounted on the mounting surface on the side of the stator of the printed circuit board and detects an overheated state of the inverter IC. When the overheat detection unit detects an overheated state, the inverter IC restricts or stops a current to be supplied to the stator.

A power electronics assembly includes a semiconductor device stack having a wide bandgap semiconductor device, a semiconductor cooling chip thermally coupled to the wide bandgap semiconductor device, and a first electrode electrically coupled to the wide bandgap semiconductor device and positioned between the wide bandgap semiconductor device and the semiconductor cooling chip. The semiconductor cooling chip is positioned between a substrate layer and the wide bandgap semiconductor device. The substrate layer includes a substrate inlet port and a substrate outlet port. An integrated fluid channel system extends between the substrate inlet port and the substrate outlet port and includes a substrate fluid inlet channel extending from the substrate inlet port into the substrate layer, a substrate fluid outlet channel extending from the substrate outlet port into the substrate layer, and one or more cooling chip fluid channels extending into the semiconductor cooling chip.

The present invention is intended to provide a semiconductor module and a semiconductor device that are compatible with various rated currents. A semiconductor module includes a lead frame, and a semiconductor element joined with the lead frame. The lead frame includes a first joining structure and a second joining structure. The first joining structure includes a void part as a part at which the lead frame does not exist, and the second joining structure includes a void part as a part at which the lead frame does not exist. Each of the first joining structure and the second joining structure has a shape such that one of the first joining structure and the second joining structure complements at least part of the void part of the other assuming that the first joining structure and the second joining structure are overlapped.

A semiconductor device according to the present disclosure includes a semiconductor substrate, a first electrode provided on the semiconductor substrate, an insulating layer including a first part provided on an upper surface of the first electrode, a second electrode including a main portion and an eaves portion, the main portion being provided on the upper surface of the first electrode, the eaves portion extending over the first part and solder covering an upper surface of the main portion and a part of an upper surface of the eaves portion wherein the insulating layer includes a second part covering a part of the upper surface of the eaves portion, the part being closer to an end portion of the eaves portion than the part covered by the solder and a third part connecting the first part and the second part and covering the end portion of the eaves portion.

A method of manufacturing a multi-layer wafer is provided. Under bump metallization (UMB) pads are created on each of two heterogeneous wafers. A conductive means is applied above the UMB pads on at least one of the two heterogeneous wafers. The two heterogeneous wafers are low temperature bonded to adhere the UMB pads together via the conductive means. At least one stress compensating polymer layer may be applied to at least one of two heterogeneous wafers. The stress compensating polymer layer has a polymer composition of a molecular weight polymethylmethacrylate polymer at a level of 10-50% with added liquid multifunctional acrylates forming the remaining 50-90% of the polymer composition.