Provided is a resin composition for encapsulation used for encapsulating a power semiconductor element formed from SiC, GaN, Ga.sub.2O.sub.3, or diamond, the resin composition for encapsulation including a thermosetting resin (A) and silica (B), in which the silica (B) includes Fe, the content of Fe is equal to or less than 220 ppm with respect to the total amount of the silica (B), and the resin composition is in a granular form, a tablet form, or a sheet form.

A semiconductor device includes a conductive pattern and a plurality of semiconductor chips. The conductive pattern is provided on an insulating substrate. The plurality of semiconductor chips is mounted on the conductive pattern. The plurality of semiconductor chips includes a first semiconductor chip and two or more second semiconductor chips electrically connected in parallel to each other. The first semiconductor chip is more likely to be affected by thermal interference than the two or more second semiconductor chips. A thickness of the conductive pattern immediately below the first semiconductor chip is larger than a thickness of the conductive pattern immediately below each of the two or more second semiconductor chips.

An improved structure for reducing compound semiconductor wafer distortion comprises a contact metal layer formed on a bottom surface of a compound semiconductor wafer, at least one stress balance layer formed on a bottom surface of the contact metal layer and made of nonconductive material, stress balance layer via holes and a die attachment layer. Each stress balance layer via hole penetrates the stress balance layer. The die attachment layer is made of conductive material, formed on a bottom surface of the stress balance layer and an inner surface of each stress balance layer via hole, and electrically connected with the contact metal layer through the stress balance layer via holes. By locating the stress balance layer between the contact metal layer and the die attachment layer, the stress suffered by the compound semiconductor wafer is balanced so that the distortion of the compound semiconductor wafer is reduced.

A semiconductor device provided with first and second semiconductor element each having an obverse and a reverse surface with a drain electrode, source electrode and gate electrode provided on the obverse surface. The semiconductor device is also provided with a control element electrically connected to the gate electrodes of the respective semiconductor elements, and with a plurality of leads, which include a first lead carrying the first semiconductor element, a second lead carrying the second semiconductor element, and a third lead carrying the control element. The first and second leads overlap with each other as viewed in a first direction perpendicular to the thickness direction of the semiconductor device, and the third lead overlaps with the first and second leads as viewed in a second direction perpendicular to the thickness direction and the first direction.

Provided is a resin composition for encapsulation used for encapsulating a power semiconductor element formed from SiC, GaN, Ga.sub.2O.sub.3, or diamond, the resin composition for encapsulation including a thermosetting resin (A) and silica (B), in which the silica (B) includes Fe, the content of Fe is equal to or less than 220 ppm with respect to the total amount of the silica (B), and the resin composition is in a granular form, a tablet form, or a sheet form.

According to one embodiment, a metallic particle paste includes a polar solvent and particles dispersed in the polar solvent and containing a first metal. A second metal different from the first metal is dissolved in the polar solvent.

According to one embodiment, a metallic particle paste includes a polar solvent and particles dispersed in the polar solvent and containing a first metal. A second metal different from the first metal is dissolved in the polar solvent.

In a heat insulating load jig 11 of the present invention, a solder material 14 having a melting point or a solidus temperature in a range between a thermal resistance temperature of a semiconductor chip 13 and a temperature 100 C. below the thermal resistance temperature is interposed between a circuit board 12 and the semiconductor chip 13; a heat insulating body 17 is placed on an upper side of the semiconductor chip 13 in this state; a metal weight 16 is disposed on the heat insulating body 17; and load is applied to the semiconductor chip 13 while the solder material 14 is melted and solidified.

In a heat insulating load jig 11 of the present invention, a solder material 14 having a melting point or a solidus temperature in a range between a thermal resistance temperature of a semiconductor chip 13 and a temperature 100 C. below the thermal resistance temperature is interposed between a circuit board 12 and the semiconductor chip 13; a heat insulating body 17 is placed on an upper side of the semiconductor chip 13 in this state; a metal weight 16 is disposed on the heat insulating body 17; and load is applied to the semiconductor chip 13 while the solder material 14 is melted and solidified.

A power chip, includes a metal region; a wafer region. The wafer region includes at least one first partition, forming a first power switch; and at least one second partition, forming a second power switch. The first power switch and the second power switch are electrically connected, a total number of the at least one first partition and the at least one second partition is not less than 3, and the at least one first partition and the at least one second partition are disposed alternatively along a curve.