A semiconductor device package includes a dielectric layer and a stacking conductive structure. The dielectric layer includes a first surface. The stacking conductive structure is disposed on the first surface of the dielectric layer. The stacking conductive structure includes a first conductive layer disposed on the first surface of the dielectric layer, and a second conductive layer stacked on the first conductive layer. A first surface roughness of the first surface of the dielectric layer is larger than a second surface roughness of a top surface of the first conductive layer, and the second surface roughness of the top surface of the first conductive layer is larger than a third surface roughness of a top surface of the second conductive layer.

An electronic circuit to which the present invention is applied has a configuration in which a first substrate and a second substrate are stacked and connected to each other. The electronic circuit includes: a transmission path configured to connect a first wiring line for a signal formed in the first substrate and a second wiring for a signal formed in the second substrate to each other; and a short-circuit stub configured to connect a ground conductor provided in the first substrate and the transmission path to each other through use of three or more types of conductors.

A high-frequency module 1a includes: a circuit board 2; a first component 3a, which has characteristics likely to be changed by heat, and a second component 3b, which generates heat, that are mounted on an upper surface 20a of the circuit board 2; a sealing resin layer 4 configured to cover each of the components 3a and 3b and a component 3c; a shield film 5 configured to cover a surface of the sealing resin layer 4; and a heat dissipation member 6 disposed above an upper surface 4a of the sealing resin layer 4. A recessed portion 11 is formed in the upper surface 4a of the sealing resin layer 4 as viewed in a direction perpendicular to the upper surface 20a of the circuit board 2. The recessed portion 11 can prevent the heat generated from the second component 3b from affecting the first component 3a.

A semiconductor package includes a semiconductor chip including an electrode pad formed on the top surface thereof, a passive device embedded in the semiconductor package, the passive device having no functional electrode on the top surface thereof, a cover layer covering the semiconductor chip and the passive device, and at least one electrode pattern formed on the cover layer to transmit electrical signals. The cover layer includes at least one first opening formed to expose a region in which the functional electrode is to be formed. The electrode pattern includes a functional electrode portion formed in a region in which the functional electrode of the passive device is to be formed through the first opening. In the process of forming the electrode pattern, a functional electrode of the passive device is formed together therewith, thereby eliminating a separate step of manufacturing a functional electrode and thus reducing manufacturing costs.

An apparatus includes: a transistor including an input terminal for an input signal and an output terminal for an output signal; a matching circuit configured to match a load impedance regarding a fundamental harmonic of at least one of the input signal and the output signal to an impedance of the transistor and include a first conductive film being laminated over the transistor and coupled to at least one of the input terminal and the output terminal; and a processing circuit configured to adjust an impedance regarding a harmonic of at least one of the input signal and the output signal and include a second conductive film being laminated over the first conductive film and coupled to at least one of the input terminal and the output terminal through a via which penetrates through a dielectric layer sandwiched between the first conductive film and the second conductive film.

A semiconductor package including a metal base, a side wall, and at least one metal lead is disclosed. The metal base has a main surface to mount at least one semiconductor element. The side wall has a frame shape and is disposed on the main surface. The side wall includes a first side wall portion made of a resin and a second side wall portion made of a resin. The second side wall portion is placed on the first side wall portion and joined to the first side wall portion with an adhesive. The metal lead is partially sandwiched between the first side wall portion and the second side wall portion. A first end of the metal lead is exposed inside of the side wall, and a second end of the metal lead is located outside of the side wall.

An optical module includes an optical semiconductor chip including a first electrode pad, a second electrode pad, and a third electrode pad arranged between the first electrode pad and the second electrode pad, a wiring substrate on which the optical semiconductor chip is flip-chip mounted, including a fourth electrode pad, a fifth electrode pad, and a sixth electrode pad arranged between the fourth electrode pad and the fifth electrode pad, a first conductive material connecting the first electrode pad with the fourth electrode pad, a second conductive material connecting the second electrode pad with the fifth electrode pad, a third conductive material arranged between the first conductive material and the second conductive material, connecting the third electrode pad with the sixth electrode pad, and a resin provided in an area on the second conductive material side of the third conductive material between the optical semiconductor chip and the wiring substrate.

A field effect transistor includes: a semiconductor region including a first inactive region, an active region, and a second inactive region arranged side by side in a first direction; a gate electrode, a source electrode, and a drain electrode on the active region; a gate pad on the first inactive region; a gate guard on and in contact with the semiconductor region, the gate guard being apart from the gate pad and located between an edge on the first inactive region side of the semiconductor region and the gate pad; a drain pad on the second inactive region; a drain guard on and in contact with the semiconductor region, the drain guard being apart from the drain pad and located between an edge on the second inactive region side of the semiconductor region and the drain pad; and a metal film electrically connected to the gate guard.

A transistor (2) is provided on a surface of a semiconductor substrate (1). First and second wirings (10,11) are provided on the surface of the semiconductor substrate (1) and sandwich the transistor (2). Plural wires (20) pass over the transistor (2) and are connected to the first and second wirings (10,11). A sealing material (21) sealing the transistor (2), the first and second wirings (10,11), and the plural wires (20). The sealing material (21) contains a filler (21a). An interval distance between the plural wires (20) is smaller than a particle diameter of the filler (21a). The sealing material (21) does not intrude into a space between the plural wires (20) and the transistor (2) so that a cavity (22) is formed.

A method of manufacturing a component-embedded substrate includes a resist forming step in which a patterning resist is formed on a support, a patterning step in which a through hole extending through the resist is formed by performing patterning on the resist, a first-electrode forming step in which a through-via electrode is formed by filling the through hole with an electrode material, a resist removing step in which the resist is removed, a component placement step in which an electronic component is placed, a substrate forming step in which a resin substrate is formed by sealing the electronic component with a resin that includes a filler having a diameter larger than the surface roughness of a side surface of the through-via electrode, and a removing step in which the support is removed from the resin substrate. The first-electrode forming step is performed before the substrate forming step is performed.