A transistor (2) is provided on a surface of a semiconductor substrate (1). First and second wirings (10,11) are provided on the surface of the semiconductor substrate (1) and sandwich the transistor (2). Plural wires (20) pass over the transistor (2) and are connected to the first and second wirings (10,11). A sealing material (21) sealing the transistor (2), the first and second wirings (10,11), and the plural wires (20). The sealing material (21) contains a filler (21a). An interval distance between the plural wires (20) is smaller than a particle diameter of the filler (21a). The sealing material (21) does not intrude into a space between the plural wires (20) and the transistor (2) so that a cavity (22) is formed.

Provided is a SiC semiconductor element equipped with a SiC integrated circuit having a stable characteristic, which operates normally even in a radiation environment. A radiation resistant circuit device includes: a SiC semiconductor element equipped with a SiC integrated circuit, a printed board on which the SiC semiconductor element is provided, a conductive wiring that is arranged inside the printed board and has a predetermined surface facing a bottom surface of a substrate electrode of the SiC integrated circuit, and an insulating material arranged between the bottom surface of the substrate electrode of the SiC integrated circuit and the predetermined surface of the conductive wiring.

An optoelectronic device includes an optical integrated circuit having a first surface and a second surface opposite the first surface. The optical integrated circuit has an optical zone of the first surface of the optical integrated circuit. The device includes an electrically insulating material disposed over the optical integrated circuit, where he electrically insulating material partially covers the first surface so as to expose the optical zone.

Provided is a SiC semiconductor element equipped with a SiC integrated circuit having a stable characteristic, which operates normally even in a radiation environment. A radiation resistant circuit device includes: a SiC semiconductor element equipped with a SiC integrated circuit, a printed board on which the SiC semiconductor element is provided, a conductive wiring that is arranged inside the printed board and has a predetermined surface facing a bottom surface of a substrate electrode of the SiC integrated circuit, and an insulating material arranged between the bottom surface of the substrate electrode of the SiC integrated circuit and the predetermined surface of the conductive wiring.

A multiple-path amplifier (e.g., a Doherty amplifier) includes a first transistor (e.g., a main amplifier FET), a second transistor (e.g., a peaking amplifier FET), a combining node, and a shunt-inductance circuit. The first and second amplifiers and the combining node structure are integrally-formed with a semiconductor die, and the shunt-inductance circuit is integrated with the die. Outputs of the first and second transistors are electrically coupled to the combining node structure. The shunt-inductance circuit is electrically coupled between the combining node structure and a ground reference node. The shunt-inductance circuit includes a shunt inductance (e.g., including wirebond(s) and/or spiral inductor(s)) that is integrated with the semiconductor die. The multiple-path amplifier also may include an integrated phase shifter/impedance inverter coupled between the outputs of the first and second transistors, and which is configured to impart a 90-degree phase delay between intrinsic drains of the first and second transistors.

A semiconductor package includes a substrate having thereon a high-frequency chip and a circuit component susceptible to high-frequency signal interference; a ground pad on the and between the high-frequency chip and the circuit component; a metal-post reinforced glue wall on the ground pad; a molding compound surrounding the metal-post reinforced glue wall and surrounding the high-frequency chip and the circuit component; and a conductive layer disposed on the molding compound and in contact with the metal-post reinforced glue wall. The metal-post reinforced glue wall comprises first metal posts and glue attached to the first metal posts. An interface between a base of each of the first metal posts and the ground pad has a root mean square (RMS) roughness that is less than 1.0 micrometer.

A package structure is disclosed, the package structure includes a substrate, a chip, a bonding layer, and a coating. A plurality of grooves are disposed on the substrate. Silver bonding materials are disposed in the grooves and on a surface of the substrate, to form the bonding layer. The chip is connected to the substrate by using the bonding layer. The grooves are symmetrically arranged along a first and a second axis that are perpendicular to each other, a vertical projection of the chip on the substrate is centrosymmetric about the first and the second axis, and the vertical projection of the chip on the substrate covers a partial area of an outer-ring groove which faces a periphery of the chip. The coating covers a surface that is of the bonding layer and not in contact with the substrate or the chip, used to prevent migration of silver ions.

A transistor (2) is provided on a surface of a semiconductor substrate (1). First and second wirings (10,11) are provided on the surface of the semiconductor substrate (1) and sandwich the transistor (2). Plural wires (20) pass over the transistor (2) and are connected to the first and second wirings (10,11). A sealing material (21) sealing the transistor (2), the first and second wirings (10,11), and the plural wires (20). The sealing material (21) contains a filler (21a). An interval distance between the plural wires (20) is smaller than a particle diameter of the filler (21a). The sealing material (21) does not intrude into a space between the plural wires (20) and the transistor (2) so that a cavity (22) is formed.

An electronic component is provided. The electronic component includes a substrate, an III-V die and a silicon die. The III-V die is disposed on the substrate. The silicon die is stacked to the III-V and electrically connected to the III-V die.

The present invention provides a semiconductor device including an insulating layer, a conductive layer bonded to one main surface of the insulating layer, a semiconductor element arranged such that the upper surface of the semiconductor element faces a direction same as the one main surface of the insulating layer, an upper electrode provided on the upper surface of the semiconductor element, a wiring member that has one end electrically bonded to the upper electrode of the semiconductor element and has another end electrically bonded to the conductive layer, and has a hollow portion, a first sealing material, and a second sealing material, in which the first sealing material seals at least part of the semiconductor element so as to be in contact with the semiconductor element, and the second sealing material seals the wiring member so as to be in contact with the wiring member.