Patent classifications
H02M3/072
Charging circuit, terminal and charging method
The present disclosure discloses a charging circuit, a terminal and a charging method, and belongs to a field of electronic circuit technologies. The charging circuit includes: a control circuit and a voltage reduction circuit connected to the control circuit; wherein the control circuit is configured to obtain a feedback signal indicating a generation frequency of a control signal, generate the control signal based on the feedback signal, and send the control signal to the voltage reduction circuit; and the voltage reduction circuit is configured to obtain an input voltage and the control signal, perform voltage reduction processing on the input voltage based on the control signal and output an output voltage to a battery, wherein an output current corresponding to the output voltage is greater than an input current corresponding to the input voltage, and the output voltage is configured to determine the generation frequency.
Compact power conversion device with continuous output regulation range
The current invention relates to a power conversion device (10), for supplying a load (11) with a PWM signal through an inductive output filter (105). The power conversion device (10) comprises a power conversion module (101) supplied by a DC input voltage (Vin) and is configured for providing a plurality of output signals (PWM1, . . . , PWMn) having a level amplitude that is a fraction of the input voltage (Vin) level. Each output signal is floating with a bias component equally split in a plurality of steps ranging from a determined lowest fraction level amplitude to a determined highest fraction level amplitude. The power conversion device (10) further comprises a multiplexer (103) receiving as a plurality of inputs the plurality of output signals (PWM1, . . . , PWMn). The multiplexer is configured for outputting one output signal (PWMx) selected from the plurality of inputs, whereby the output signal (PWMx) of the multiplexer (103) is connected to the output filter (105).
CIRCUIT ARCHITECTURE FOR A MEASURING ARRANGEMENT, A LEVEL CONVERTER CIRCUIT, A CHARGE PUMP STAGE AND A CHARGE PUMP, AND METHOD FOR OPERATING SAME
In various embodiments, a measuring arrangement is provided. The measuring arrangement may include a micromechanical sensor including a capacitor, a bridge circuit including a plurality of capacitors, at least one capacitor of which is the capacitor of the micromechanical sensor, an amplifier coupled, on the input side, to an output of the bridge circuit, a DC voltage source configured to provide an electrical DC voltage, a chopper including at least one first charge store and a switch structure, The switch structure is configured to couple the first charge store alternately to the DC voltage and the bridge circuit for the purpose of coupling an electrical mixed voltage into the bridge circuit.
System and method for reducing power loss in switched-capacitor power converters
A system for reducing power loss in a switched-capacitor converter includes a first and second switched capacitor sub-converter each having a flying capacitor and a first, second, third, and fourth switching device. Each switching device is controlled by one of a first, second, third, and fourth clock signal. The first, second, third and fourth clock signals of the second switched capacitor sub-converter are inverted such that the first switched capacitor sub-converter operates during a first phase and the second switched capacitor converter operates during a second phase that is 1800 degrees out of phase from the first phase. The system also includes a resonant charge sharing portion for coupling a bottom-plate parasitic capacitance of the first switched capacitor sub-converter to a bottom-plate parasitic capacitance of the second switched capacitor converter.
Circuits and methods for controlling a three-level buck converter
A circuit including: a control system for a three-level buck converter, the three-level buck converter including multiple input switches, each of the input switches receiving one of a plurality of different pulse width modulated signals, the control system including: a first clock signal and a second clock signal, the second clock signal being a phase-shifted version of the first clock signal; ramp generating circuitry receiving the first and second clock signals and producing first and second ramp signals, respectively, from the first and second clock signals; a first comparing circuit receiving the first ramp signal and producing a first one of the pulse width modulated signals therefrom; and a second comparing circuit receiving the second ramp signal and producing a second one of the pulse width modulated signals therefrom.
Charge pump regulation circuit to increase program and erase efficiency in nonvolatile memory
A charge pump circuit generates a charge pump output signal at a first node and is enabled by a control signal. A diode has an anode coupled to the first node and a cathode coupled to a second node. A current mirror arrangement sources a first current to the second node and sinks a second current from a third node. A comparator causes the control signal to direct the charge pump circuit to generate the charge pump output signal as having a voltage that ramps upwardly in magnitude (but negative in sign) if the voltage at the second node is greater than the voltage at the third node, and causes the control signal to direct the charge pump circuit to cease the ramping of the voltage of the charge pump output signal if the voltage at the second node is at least equal to the voltage at the third node.
ELECTRICAL CIRCUIT FOR VOLTAGE CONVERSION
A circuit includes a second voltage converter electrically coupled to a comparator and first voltage converter. The first voltage converter receives first and second clocks and an input signal at a first voltage and generates an intermediate signal at a second voltage based on the input signal and the first and second clocks. The second voltage converter receives the intermediate signal, the second clock, and a comparison signal and generates an output signal at a third voltage based on the intermediate and comparison signals and the second clock. The comparator receives a reference voltage, the output signal, and the first clock, compares the reference voltage and output signal, and generates the comparison signal based on the first clock and the comparison of the reference voltage and output signal. The second voltage converter adjusts the third voltage of the output signal to approach the reference voltage based on the comparison signal.
Internal voltage generation circuit and semiconductor device including the same
An internal voltage generation circuit includes a first control signal generation unit suitable for generating a first control signal activated to a level of a second external voltage when a first external voltage is activated, a second control signal generation unit suitable for generating a second control signal that equals the higher of the second external voltage and an internal voltage, and a voltage generation unit suitable for generating the internal voltage by performing a charge pumping operation based on the second external voltage and an oscillation signal while blocking a current flowing through a generation node from which the internal voltage is generated, based on the first and second control signals.
Charge pump circuit
A bipolar output charge pump circuit having a network of switching paths for selectively connecting an input node and a reference node for connection to an input voltage, a first pair of output nodes, two pairs of flying capacitor nodes, and a controller for controlling the switching of the network of switching paths. The controller is operable to control the network of switching paths when in use with two flying capacitors connected to the two pairs of flying capacitor nodes, to provide a first mode and a second mode when in use with two flying capacitors connected to the flying capacitor nodes, where at least the first mode corresponds to a bipolar output voltage of +/−3VV, +/−VV/5 or +/−VV/6.
Step-down circuit
A step-down circuit includes a first transistor of N-type having a channel between an input terminal and a first node, and a gate to which a reference voltage that is lower than a peak value of an AC voltage applied to the input terminal is applied, a second transistor of P-type having a channel between the input terminal and a second node, and a gate to which the reference voltage is applied, a third transistor of N-type having a channel between the first node and an output terminal, and a gate to which the AC voltage is applied, a fourth transistor of P-type having a channel between the second node and the output terminal, and a gate to which the AC voltage is applied, a first capacitor connected between the first node and the second node, and a second capacitor connected between the output terminal and a reference potential terminal.