Provided is a regulator circuit that supplies an output voltage to a load, the regulator circuit including an error amplifier that amplifies an error between a feedback signal and a reference voltage, and an output stage that changes the output voltage, the error amplifier including a first transconductance amplifier that receives the feedback signal and the reference voltage, a first resistance connected to an output node of the first transconductance amplifier and a ground, a first capacitor connected in parallel to the first resistance, a second transconductance amplifier that receives a voltage of the output node of the first transconductance amplifier and the feedback signal, a second resistance connected to an output node of the second transconductance amplifier and a ground, a second capacitor connected in parallel to the second resistance, and a zero controller that controls a gain of the second transconductance amplifier.

The present disclosure relates to a semiconductor device and a cell potential measuring device capable of improving measurement accuracy of a potential of a solution.A semiconductor device includes a read electrode that reads a potential of a solution, a differential amplifier, a first capacitor connected in series in a loop feeding back an output of the differential amplifier to a second input different from a first input from the read electrode, a resistance element connected in parallel with the first capacitor, and a second capacitor connected between a reference electrode indicating a reference potential and the second input. The present disclosure can be applied to, for example, a cell potential measuring device.

A multi-stage amplifier circuit includes: a front stage amplification circuit, for generating a front stage amplification signal according to a difference between a primary reference signal and a primary feedback signal; an output adjustment circuit, for generating a driving signal according to the front stage amplification signal; and an output transistor, controlled by the driving signal to generate an output signal. The output adjustment circuit includes: an adjustment transistor biased by a differential current of the front stage amplification signal; and an impedance adjustment device biased by the differential current. A resistance of the impedance adjustment device is determined by a difference between an adjustment feedback signal and an adjustment reference signal. The driving signal is determined by a product of a resistance of the impedance adjustment device multiplied by the differential current of the front stage amplification signal, and a drain-source voltage of the adjustment transistor.

A low-dropout voltage regulator is provided. The low-dropout voltage regulator includes a differential amplifier pair, a secondary amplification circuit that is self-stabilized, an output circuit, and a frequency compensation circuit. The secondary amplification circuit includes a first amplification transistor and a second amplification transistor. The first amplification transistor includes a first terminal, a second terminal, and a third terminal. The second amplification transistor includes a first terminal, a second terminal, and a third terminal. The second terminal of the first amplification transistor is electrically connected to the second terminal of the second amplification transistor to form an input terminal of the secondary amplification circuit to be connected to an output terminal of the differential amplifier pair. The frequency compensation circuit is disposed between an output terminal of the secondary amplification circuit, a second terminal of an output transistor, and a third terminal of the output transistor.

An amplifier including a P-channel transistor having current terminals coupled between a first node and a second node and having a control terminal coupled to a third node receiving an input voltage, an N-channel transistor having current terminals coupled between a fourth node developing an output voltage and a supply voltage reference and having a control terminal coupled to the second node, a first resistor coupled between the first node and a supply voltage, a second resistor coupled between the first and fourth nodes, and a current sink sinking current from the second node to the supply reference node. The amplifier may be converted to differential form for amplifying a differential input voltage. Current devices may be adjusted for common mode, and may be moved or added to improve headroom or to improve power supply rejection. Chopper circuits may be added to reduce 1/f noise.

Various embodiments provide for active suppression circuitry. The active suppression circuitry can be used with a circuit for a memory system, such as a dual data rate (DDR) memory system. For example, some embodiments provide an active suppression integrated circuit. The active suppression integrated circuit can be used by a memory system to efficiently suppress power supply noise caused by resonance of a power delivery network (PDN) of the memory system, thereby improving power integrity of the memory system input/output.

Monolithic microwave integrated circuits (MMICs) tolerant to electrical overstress are provided. In certain embodiments, a MMIC includes a signal pad that receives a radio frequency (RF) signal, and an RF circuit coupled to the RF signal pad. The RF circuit includes a transistor layout, an input field-effect transistor (FET) implemented using a first portion of a plurality of gate fingers of the transistor layout, and an embedded protection device electrically connected between a gate and a source of the input FET and implemented using a second portion of the plurality of gate fingers. The MMIC is tolerant to electrical overstress events, such as field-induced charged-device model (FICDM) events.

A power amplifier circuit including a plurality of analog power amplifiers configured to generate a output power for an output signal; at least one processor configured to: select a highest output power signal; determine an input signal power of a modulated signal; determine an output signal power based on the input signal power; compare the output signal power and the highest output power; and disable a subset of the plurality of analog power amplifiers based on the comparison, wherein a remainder of the plurality of analog power amplifiers are configured to generate the output signal power.

A semiconductor integrated circuit has a reception circuit configured to receive a strobe signal of which a logic is intermittently switched in synchronization with a data signal, an output circuit configured to extract a low frequency component including at least a DC component of the strobe signal received by the reception circuit and to output a first signal, and a comparison circuit configured to compare a signal level of the first signal with a threshold level. The reception circuit is configured to change a boost amount of a high frequency component different from the low frequency component of the strobe signal based on a comparison result obtained by the comparison circuit.

This application relates to method and apparatus for driving acoustic transducers, such as speakers or haptic transducers. A transducer driver circuit (200) has a hysteretic comparator (201) configured to compare, with hysteresis, an input signal (S.sub.IN) received at a first comparator input to a feedback signal (S.sub.FB) received at a second comparator input. Based on the comparison the hysteretic comparator (201) generates a pulse-width modulation (PWM) signal (S.sub.PWM) at a comparator output (206). An inductor (203) is coupled between the comparator output and an output node (204). In use a resistive component (208), which may comprise the transducer (301) is coupled to output node (204). The inductor (203) and resistive component (208) provide filtering to the PWM signal (S.sub.PWM). A feedback path extends between the output node (204) and the second comparator input to provide the feedback signal (S.sub.FB).