An integrated circuit includes: an amplifier circuit including a first inverter and a second inverter to amplify a voltage difference between a first line and a second line; a replica amplifier circuit including a first replica inverter having an input terminal and an output terminal which are coupled to a second replica line and replicating the first inverter, and that includes a second replica inverter having an input terminal and an output terminal which are coupled to a first replica line and replicating the second inverter; and a current control circuit suitable for controlling an amount of a current sourced to the replica amplifier circuit and an amount of a current sunken from the replica amplifier circuit based on comparison of an average level between a voltage of the first replica line and a voltage of the second replica line with a level of a target voltage.

The invention provides a Low-voltage Differential Signaling (LVDS) receiver circuit that comprises a folded-cascode operational transconductance amplifier (OTA) that includes a pair of input branches and a pair of output branches. The pair of input branches of the folded-cascode OTA includes a p-channel metal-oxide semiconductor (PMOS) input transistor pair connected to a first supply voltage domain. The pair of output branches includes an output circuit connected to a second supply voltage domain. The LVDS receiver circuit further includes a common-mode feedback circuit connected to the pair of output branches of the folded-cascode OTA that controls the second supply voltage domain. The LVDS receiver circuit further includes a regenerative buffer circuit connected to the pair of output branches of the folded-cascode OTA and an output generated from the pair of output branches of the folded-cascode OTA directly operates the regenerative buffer circuit to produce a distortion-free output signal.

An input/output circuit may include an input circuit, an amplifier circuit and a precharging circuit. The input circuit may load differential input data to setup nodes based on a data strobe clock. The amplifier circuit may compare and amplify the data that is loaded to the setup nodes and configured to output the amplified data. The precharging circuit may precharge the setup nodes based on the data strobe clock and the differential input data.

A buffer circuit according to an aspect of the inventive concepts include an operational amplifier configured to amplify an input voltage to generate an output voltage; a slew-rate compensating circuit configured to generate a compensation current based on a difference between a voltage level of the input voltage and a voltage level of the output voltage, and configured to provide the compensation current to the operational amplifier through a boosting transistor; and an offset blocking circuit configured to turn off the boosting transistor when the difference between the voltage level of the input voltage and the voltage level of the output voltage is less than a reference voltage level by providing a blocking current to the slew-rate compensating circuit.

A down-conversion mixer includes a trans conductance circuit and a mixing circuit. The transconductance circuit includes: first and second transconductance units cooperatively converting a differential input voltage signal pair into a differential input current signal pair; and an inductor coupled between the first and second transconductance units. The mixing circuit is coupled to a common node of the first trans conductance unit and the inductor and to a common node of the second transconductance unit and the inductor for receiving the differential input current signal pair therefrom, and mixes the differential input current signal pair with a differential oscillatory voltage signal pair to generate a differential mixed voltage signal pair.

Circuits and methods for achieving good AM-AM and AM-PM metrics while achieving good power, PAE, linearity, and EVM performance in an amplifier. Embodiments provide an equalization approach which compensates for AM-AM and AM-PM variations in an amplifier by controlling bias voltage versus output power to alter the AM-AM and AM-PM profiles imposed by the amplifier. Differential amplifier embodiments include cross-coupled common-gate transistors that generate an equalization voltage that alters the gate bias voltage of respective main FETs in proportion to a power level present at the respective drains of the main FETs. Single-ended amplifier embodiments include an equalization circuit that alters the bias voltage to the gate of a main FET in proportion to a power level present at the main FET drain. Embodiments may also include a linearization circuit which alters the AM-PM profile of an input signal to compensate for the AM-PM profile imposed by a coupled amplifier.

A voltage regulator includes a first switch connected between a first input terminal of an error amplifier circuit and an input terminal of the voltage regulator, a second switch connected between a second input terminal of the error amplifier circuit and an output terminal of the voltage regulator, a third switch connected between the first input terminal and the second input terminal, and a short fault detection circuit which detects a short fault of the output terminal, based on an output voltage of the voltage regulator.

Disclosed is an amplifier including a first transistor and a second transistor to which differential input signals are applied to gate terminals thereof, respectively, a second transistor having a first end connected to the first transistor, a gate terminal receiving a first bias signal, and a second end outputting a first differential output signal of a differential output signal pair, a fourth transistor having a first end connected to the second transistor, a gate terminal receiving a second bias signal, and having a second end outputting the a second differential output signal, and a pair of capacitors coupled to the second transistor and the fourth transistor, and having a cross-coupled structure with respect to each other.

A ripple pre-amplification based fully integrated LDO pertains to the technical field of power management. The positive input terminal of a transconductance amplifier is connected to a reference voltage Vref, and the negative input terminal of the transconductance amplifier is connected to the feedback voltage V.sub.fb. The output terminal of the transconductance amplifier is connected to the negative input terminal of a transimpedance amplifier and the negative input terminal of an error amplifier. The positive input terminal of the transimpedance amplifier is connected to the ground GND, and the output terminal of the transimpedance amplifier is connected to the positive input terminal of the error amplifier. The gate terminal of the power transistor M.sub.P is connected to the output terminal of the error amplifier, the source terminal of the power transistor M.sub.P is connected to an input voltage V.sub.IN, and the drain terminal of the power transistor M.sub.P is grounded.

A down-conversion mixer includes a trans conductance circuit and a mixing circuit. The transconductance circuit includes: first and second transconductance units cooperatively converting a differential input voltage signal pair into a differential input current signal pair; and an inductor coupled between the first and second transconductance units. The mixing circuit is coupled to a common node of the first trans conductance unit and the inductor and to a common node of the second transconductance unit and the inductor for receiving the differential input current signal pair therefrom, and mixes the differential input current signal pair with a differential oscillatory voltage signal pair to generate a differential mixed voltage signal pair.