An apparatus for temperature sensing may include: a bias generator suitable for generating a complementary-to-absolute-temperature (CTAT) bias voltage; a regulator suitable for regulating a bias voltage by using CTAT bias voltage and outputting a regulated bias voltage; and a ring oscillator suitable for receiving the regulated bias voltage and generating an oscillation signal based on the regulated bias voltage.

Differing from conventional oscillator circuit does not include temperature compensation function, the present invention particularly constitutes a gain stage, a current mirror unit, a clamping current supplying unit, a noise inhibiting unit, a compensation unit, and a reference signal generating unit to a novel oscillator circuit having temperature compensation function. A variety of experimental data have proved that, based on the normal operation of the compensation unit and the reference signal generating unit, the oscillator frequency of the oscillator circuit of the present invention almost be kept at same level even if the ambient temperature continuously increases. Therefore, because the frequency drift due to temperature variation would not occur in the oscillator circuit of the present invention, the novel oscillator circuit is potential oscillator to replace the conventional oscillators applied in analog-to-digital convertors or time-to-digital convertors.

Oscillation ring circuits and apparatuses and methods for measuring reading time of sequential circuit are provided. An oscillation ring circuit includes an odd number of oscillatory circuits connected in series, each including a first clock generator circuit, a flip-flop circuit and a first inverter circuit connected in series. Within an oscillatory circuit, output end of clock generator circuit is connected to clock signal input end of flip-flop circuit; data output end of flip-flop circuit is connected to input end of first inverter circuit; output end of first inverter circuit is connected to input end of first clock generator circuit and data input end of flip-flop circuit within another oscillatory circuit. Another oscillation ring circuit is formed by replacing one flip-flop circuit with a sequential circuit to be measured. Reading time of the sequential circuit is measured according to changes in waveforms of oscillation periods of oscillation ring circuits.

The phase-lock loop (PLL) can include a variable frequency oscillator adjustable to control the phase of the output signal; a primary control subsystem including a phase detector and a connection between the output signal and the phase detector, the phase detector generating a primary control signal to adjust the variable frequency oscillator; and a secondary control subsystem having an analog-to-digital converter and a digital-to-analog converter connected in series to receive the primary control signal and generate a secondary control signal also connected to independently adjust the variable frequency oscillator.

A circuit includes a first and second oscillator, a first and second phase comparator, and a control unit. The first and second oscillators are configured to respectively generate a first and second oscillating signal. The first and second phase comparators are connected between the first and second oscillators. The first phase comparator is configured to generate a first phase error signal according to a first signal associated with the first oscillating signal and a delayed version of a second signal associated with the second oscillating signal. The second phase comparator is configured to generate a second phase error signal according to the second signal and a delayed version of the first signal. The control unit is connected between the first and second phase comparators and configured to generate one of a tuning signal and a pulse signal based on the difference between the first and second phase error signals.

The present invention relates to passive phased injection locked circuit and ring-based voltage controlled oscillators. passive phased injection locked circuit comprises first and second transmission lines, each has a plurality of discrete elements, that are operative to deley the phase of AC signal. Between the first and second transmission lines, a capacitor network is formed to advance the phases of the AC signal in concert along the transmission lines. For the ring-based voltage controlled oscillators, each of the first and second transmission lines has an odd number of discrete elements.

A system includes a first phase interpolator, a second phase interpolator, and a circuit. The circuit is configured to receive a first signal and a second signal provided by the first phase interpolator and a third signal and a fourth signal provided by the second phase interpolator. The first circuit is configured to provide at least eight phase signals, each of the eight phase signals being at a respective phase angle in response to the first signal, the second signal, the third signal and the fourth signal.

A clock generator comprises a first capacitor, a current source, and a voltage node. A first switch is coupled between the first capacitor and the current source. A second switch is coupled between the first capacitor and voltage node.

The invention relates to a multi-phase oscillator for generating multiple phase-shifted oscillator signals including: a ring oscillator having a number of concatenated oscillator delay cells which are interconnected to generate an oscillator signal, wherein phase-shifted oscillator signals are generated between the oscillator delay cells; a phase-blending unit configured to receive two phase-shifted oscillator signals and to generate a mid-phase oscillator signal whose phase shift is between the shifts of the two phase-shifted oscillator signals; and an interpolator delay line having a number of concatenated interpolator delay cells to generate further phase-shifted oscillator signals.

A circuit includes a first and second oscillator, a first and second phase comparator, and a control unit. The first and second oscillators are configured to respectively generate a first and second oscillating signal. The first and second phase comparators are connected between the first and second oscillators. The first phase comparator is configured to generate a first phase error signal according to a first signal associated with the first oscillating signal and a delayed version of a second signal associated with the second oscillating signal. The second phase comparator is configured to generate a second phase error signal according to the second signal and a delayed version of the first signal. The control unit is connected between the first and second phase comparators and configured to generate one of a tuning signal and a pulse signal based on the difference between the first and second phase error signals.