A system includes a first phase interpolator, a second phase interpolator, and a circuit. The circuit is configured to receive a first signal and a second signal provided by the first phase interpolator and a third signal and a fourth signal provided by the second phase interpolator. The first circuit is configured to provide at least eight phase signals, each of the eight phase signals being at a respective phase angle in response to the first signal, the second signal, the third signal and the fourth signal.

An apparatus comprising a local oscillator (LO) for driving a mixer, the LO being configured to oscillate at an oscillation frequency, and generate a first set of LO signals, wherein each of the first set of LO signals has a LO signal frequency equal to a first multiplication factor m multiplied by the oscillation frequency, the first multiplication factor m, being an integer greater than or equal to two, and each of the first set of LO signals is separated by adjacent LO signals by a phase difference equal to 360 divided by a first variable n, the first variable n being an integer that is greater than or equal to two.

Techniques and mechanisms for determining calibration information based on tuning of a ring oscillator circuit formed with two integrated circuit (IC) dies. In an embodiment, an oscillator circuit comprises an in-series arrangement of delay circuits including a first one or more delay circuits of a first die, and a second one or more delay circuits of a second die. Respective circuitry of the first die and the second die performs tuning to match an oscillation frequency of the oscillator circuit with a reference frequency. An operational setting of the tuned oscillator circuit is provided to calibrate transmitter circuitry of the first die and the second die. In another embodiment, tuning of the oscillator circuit is further based on tuning of a local oscillator circuit of one of the first die or the second die.

Systems, devices, and methods are described herein for aligning a phase of a ring oscillator and removing jitter. An oscillator includes a resistor bank array, an operational amplifier, a first and second transistor, and a realignment circuit. The resistor bank array has a plurality of resistors configured to generate a first signal. The operational amplifier is coupled to a PLL circuit and is configured to compare a voltage of the PLL circuit with a voltage of the resistor bank array. The first transistor is coupled between the operational amplifier and a ring oscillator. The first transistor is configured to generate a second signal to control a frequency of the ring oscillator during a realignment state. The realignment circuit is coupled to the first transistor and the ring oscillator. The realignment circuit is configured to generate a realignment signal to align the ring oscillator with a first clock signal.

An integrated circuit device includes a digitally controlled oscillator (DCO), two charge-sharing capacitors, two charge-sharing switches, two pre-charge switches, and two DACs. The DCO has a first inverter and a second inverter. A first charge-sharing capacitor has a first terminal coupled to an input terminal of the first inverter through a first charge-sharing switch. A first DAC has an output terminal coupled to the first terminal of the first charge-sharing capacitor through a first pre-charge switch. A second charge-sharing capacitor has a first terminal coupled to an input terminal or an output terminal of the second inverter through a second charge-sharing switch. A second DAC has an output terminal coupled to the first terminal of the second charge-sharing capacitor through a second pre-charge switch.

An injection locked ring oscillator (ILRO) system is disclosed. The ILRO system includes an ILRO circuit configured to receive a plurality of injection control signals and a phase control signal, and to generate a plurality of output clock signals; a phase detector circuit configured to receive the output clock signals and to generate a phase output signal based on phase differences of particular pairs of the output clock signals; and a phase to voltage circuit configured to receive the phase output signal from the phase detector circuit, and to generate the phase control signal based on the phase output signal, where the phase control signal presents a negative feedback phase signal to the ILRO circuit for the phase differences in the particular pairs of the output clock signals.

This application provides a ring oscillator and a communication apparatus. In one example, the ring oscillator includes at least three differential inverting amplifiers that are coupled in a ring. A first output end and a second output end of each differential inverting amplifier are respectively coupled to a first input end and a second input end of a next adjacent differential inverting amplifier. The at least three differential inverting amplifiers include a first differential inverting amplifier, a first input end of the first differential inverting amplifier is coupled to a first output end of the first differential inverting amplifier, and a second input end of the first differential inverting amplifier is coupled to a second output end of the first differential inverting amplifier.

Described herein is a circuitry for enabling synchronized chopping for ring oscillators. The circuitry may include a differentially arranged pair of ring oscillators; a chopping logic configured to perform a chopping operation for the ring oscillators; and a control logic configured to: stop each ring oscillator in a predefined state; enable the chopping logic to perform the chopping operation after both ring oscillators are stopped; and restart both ring oscillators after the chopping operation is completed.

Provided is a clock generation apparatus which generates an output clock signal, comprising: a first voltage-controlled oscillator which outputs the output clock signal; an AD converter which includes: a second voltage-controlled oscillator which outputs an internal clock signal phase-locked to the output clock signal in response to a digital temperature signal having become a value corresponding to an analog temperature signal from a temperature sensor; a phase comparator which detects a phase difference between the output clock signal and the internal clock signal; and a digital temperature signal generator which generates a digital temperature signal according to the phase difference detected by the phase comparator, to output it to the second voltage-controlled oscillator; and a digital temperature compensation circuit which compensates a frequency of the output clock signal of the first voltage-controlled oscillator by using the digital temperature signal.

A method includes causing a digital controlled oscillator to oscillate in a phase locked loop having a first closed loop transfer function, and changing the phase locked loop having the first closed loop transfer function to a phase locked loop having a second closed loop transfer function. The method also includes starting a charge-sharing locking process to correct phase errors in the digital controlled oscillator while the digital controlled oscillator oscillates in the phase locked loop having the second closed loop transfer function.