A field effect transistor semiconductor device having a compact device footprint for use in automotive and hot swap applications. The device includes a plurality of field effect transistor cells with the plurality of transistor cells having at least one low threshold voltage transistor cell and at least one high threshold voltage transistor cell arranged on a substrate. The field effect transistor semiconductor device is configured and arranged to operate the at least one high threshold voltage transistor cell during linear mode operation, and operate both the low threshold voltage transistor cell and the high threshold voltage transistor cell during resistive mode operation. Further provided is a method of operating field effect transistor semiconductor device including a plurality of field effect transistor cells that includes at least one low threshold voltage transistor cell and at least one high threshold voltage transistor cell.

Disclosed herein are switching or other active FET configurations that implement a main-auxiliary branch design. Such designs include a circuit assembly for performing a switching function that includes a branch including a main path in parallel with an auxiliary path. The circuit assembly also includes a gate bias network connected to the main path and to the auxiliary path, the main path and the auxiliary path each having different structures that are configured to improve linearity of the switching function.

An output driver includes a pre-driver receiving a driver control code to generate a pull-up control signal or a pull-down control signal in response to data while a read operation is performed, an on-die termination controller receiving a first on-die termination control code to generate a first on-die termination control signal in response to an on-die termination enable signal while a write operation is performed, and a main driver including a pull-up n-channel metal-oxide-semiconductor (NMOS) driver generating high-level output data in response to the pull-up control signal while the read operation is performed, and terminating high-level input data with a first high voltage and terminating low-level input data with a first low voltage in response to the first on-die termination control signal while the write operation is performed, and a pull-down NMOS driver generating low-level output data in response to the pull-down control signal while the read operation is performed.

Disclosed herein are switching or other active FET configurations that implement a segmented main-auxiliary branch design. Such designs include a circuit assembly for performing a switching function that includes a branch including a plurality of main-auxiliary pairs coupled in series, wherein each main-auxiliary pair includes a main field-effect transistor (FET) in parallel with an auxiliary FET. The circuit assembly also includes a gate bias network connected to the main FETs and configured to bias the main FETs in a strong inversion region. The circuit assembly also includes an auxiliary bias network connected to the auxiliary FETs and configured to bias the auxiliary FETs in a weak inversion region.

An output driver includes a pre-driver receiving a driver control code to generate a pull-up control signal or a pull-down control signal in response to data while a read operation is performed, an on-die termination controller receiving a first on-die termination control code to generate a first on-die termination control signal in response to an on-die termination enable signal while a write operation is performed, and a main driver including a pull-up n-channel metal-oxide-semiconductor (NMOS) driver generating high-level output data in response to the pull-up control signal while the read operation is performed, and terminating high-level input data with a first high voltage and terminating low-level input data with a first low voltage in response to the first on-die termination control signal while the write operation is performed, and a pull-down NMOS driver generating low-level output data in response to the pull-down control signal while the read operation is performed.

A method of generating a gate drive signal for driving a control terminal of a power switch includes detecting a system input signal; determining a signal pulse of the system input signal being a first signal pulse following a power up event, or following an idle period, or following removal of a fault condition; and in response, generating a soft gate drive signal to drive the control terminal of the power switch to softly turn on the power switch. In another embodiment, the method includes determining a duration of the on period of the system input signal exceeding a maximum on duration and in response, disabling the gate drive signal to turn off the power switch; and determining a deassertion transition of the system input signal and in response, blocking the system input signal from the gate drive signal for a minimum off duration.

Disclosed herein are switching or other active FET configurations that implement a main-auxiliary branch design. Such designs include a circuit assembly for performing a switching function that includes a branch including a main path in series with an auxiliary path. The circuit assembly also includes a first gate bias network connected to the main path. The circuit assembly also includes a second gate bias network connected to the auxiliary path, the second gate bias network configured to improve linearity of the switching function.

In a semiconductor integrated circuit employing power gating, a control input signal is propagated to one or more first power switches through a first propagation path and to one or more second power switches through a second propagation path. A restoration determination circuit receives a first signal of the first propagation path and a second signal of the second propagation path and generates a control output signal. When the control signal performs restoration transition, the restoration determination circuit causes the control output signal to perform the restoration transition in accordance with a later timing of timings of restoration transitions of the first and second signals.

According to an embodiment of an electronic circuit, the electronic circuit includes a first input pin, a second input pin, an output pin, a control circuit and an output circuit. The first input pin is configured to receive a first input signal that includes an enable information and at least one operation parameter information. The second input pin is configured to receive a second input signal. The control circuit is configured to generate a drive signal based on the enable information included in the first input signal and the second input signal. The output circuit is configured to generate an output signal at the output pin such that a timing of the output signal is dependent on the drive signal and at least one parameter of the output signal is dependent on the at least one operation parameter information included in the first input signal.

A switching circuit includes: a main switch array including multiple main switch elements respectively arranged on multiple main signal paths configured in a parallel connection, wherein the multiple main signal paths are coupled with a first circuit node; a main switch control circuit for controlling the multiple main switch elements; an auxiliary switch array including multiple auxiliary switch elements respectively arranged on multiple auxiliary signal paths configured in a parallel connection, wherein the multiple auxiliary signal paths are also coupled with the first circuit node; and an auxiliary switch control circuit for controlling the multiple auxiliary switch elements so as to maintain a total number of turned-on switch elements in the main switch array and the auxiliary switch array to be equal to or more than a threshold quantity.