A switching element driving device includes a main on switch that is connected to gates of a first and second IGBTs and that, when brought into a conductive state, turns on the first and second IGBTs, diodes each disposed between the main on switch and one of the gates of the first and second IGBTs, the diodes having a forward direction from the main on switch to the gates of the first and second IGBTs, an on sub-switch that is connected to the gate of the second IGBT and that, when brought into the conductive state, turns on the second IGBT, and a control circuit that controls the conductive state and a non-conductive state of the main on switch and the on sub-switch.

Disclosed herein are switching or other active FET configurations that implement a main-auxiliary branch design. Such designs include a circuit assembly for performing a switching function that includes a branch including a main path in parallel with an auxiliary path. The circuit assembly also includes a first gate bias network connected to the main path. The circuit assembly also includes a second gate bias network connected to the auxiliary path, the second gate bias network configured to improve linearity of the switching function.

An intelligent power module includes a power switch, a freewheeling device, and a controller circuit incorporating a gate drive circuit and one or more power switch protection circuits. In one embodiment, the power switch is an insulated gate bipolar transistor (IGBT) device, the freewheeling device is a PN junction diode, and the controller circuit is implemented as a semiconductor integrated circuit (IC). The power module implements protection functions for the power switching device where the protection circuits are formed on the controller circuit IC and co-packaged with the power switch. In some embodiments, the control circuit in the power module includes an active soft-start circuit which is activated to realize soft-start of the power switch. In other embodiments, the control circuit in the power module includes an active turn-on pulse control circuit to detect for abnormal system input signal pulse events and block system undesired input pulses.

Some embodiments of the invention include a pre-pulse switching system. The pre-pulsing switching system may include: a power source configured to provide a voltage greater than 100 V; a pre-pulse switch coupled with the power source and configured to provide a pre-pulse having a pulse width of T.sub.pp; and a main switch coupled with the power source and configured to provide a main pulse such that an output pulse comprises a single pulse with negligible ringing. The pre-pulse may be provided to a load by closing the pre-pulse switch while the main switch is open. The main pulse may be provided to the load by closing the main switch after a delay T.sub.delay after the pre-pulse switch has been opened.

A method of controlling a power field-effect transistor includes controlling a plurality of different phases of a gate-to-source voltage of the power field-effect transistor. Without comparing the gate-to-source voltage of the power field effect transistor to a plurality of reference voltages, the method includes discriminating between the different phases of the gate-to-source voltage based on the plurality of reference voltages. At least one of the plurality of reference voltages is based on a threshold voltage of at least one field-effect transistor.

Disclosed herein are switching or other active FET configurations that implement a main-auxiliary branch design. Such designs include a circuit assembly for performing a switching function that includes a branch including a main path in parallel with an auxiliary path, both the main path and the auxiliary path having a plurality of field-effect transistors. The circuit assembly also includes a first gate bias network connected to the main path. The circuit assembly also includes a second gate bias network connected to a first subset of the plurality of FETs of the auxiliary path. The circuit assembly also includes a third gate bias network connected to a second subset of the plurality of FETs of the auxiliary path so that the third gate bias network switches on the auxiliary path when the main path is on for nonlinear cancellation, and switches off the auxiliary path when the main path is off to enable the branch to withstand maximum voltage swings.

This electrical switching apparatus has at least two power components each including first and second power transistors. A driver control device of the transistors is configured to deliver a first control signal to each of the first transistors and a second control signal to each of the second transistors, and an electrical interconnect device connecting the driver control device to the power components. The interconnect device includes several electrically conductive plates extending parallel to one another, each being connected between a control electrode of one of the first or second power transistors and a corresponding output of the driver control device.

In certain aspects, an apparatus includes a first plurality of power switch devices. Each of the first plurality of power switch devices includes a delay line having a programmable time delay, and a power switch coupled between a supply rail and a circuit block, wherein the power switch has a control input coupled to the delay line. The apparatus also includes a switch manager configured to program the time delays of the delay lines in the first plurality of power switch devices based on a number of active circuit blocks in a system.

A communication device, a communication system and an operation method thereof are provided. The communication device includes a micro-controller unit (MCU) and a field programmable gate array (FPGA). The FPGA is coupled to the MCU, and is configured to execute a first communication protocol to work with the MCU so as to communicate with another communication device in a first period, and meanwhile the FPGA is programmed with a second communication protocol by the MCU in the same first period. The FPGA is controlled by a switch pulse output from the MCU to terminate the first period, and switched from the first communication protocol to the second communication protocol, and then executes the second communication protocol to work with the MCU so as to communicate with the another communication device in a second period.

A switch circuit includes a first MOS transistor and a second MOS transistor of a same conductivity type connected in parallel between a first terminal and a second terminal. The first and second MOS transistors have respective gate terminals coupled to the control terminal to receive a control signal to turn the switch circuit on or off where the control signal transitions from a first voltage level to a second voltage level at a slow rate of change. The first MOS transistor has a first threshold voltage and the second MOS transistor has a second threshold voltage where the first threshold voltage is less than the second threshold voltage.