A semiconductor device connectable between a first power-supply line connected to a power source and through which power is continuously supplied to a first circuit, and a second power-supply line that is not directly connected to the power source and is connected to a second circuit, includes a first switch connectable between the first and second power-supply lines and turned on in response to a signal for supplying power to the second circuit, a second switch connectable between the first and second power-supply lines and having a current supply capability higher than the first switch, and a control circuit configured to turn on the second switch when the first switch is turned on and a voltage applied to the second power-supply line has reached a threshold.

A method includes simultaneously controlling several transistors by a first signal and separately controlling the transistors by distinct second pulsed signals.

A drive circuit for a power switching transistor includes a first pull-up drive transistor connected in parallel with a second pull-up drive transistor, a first pull-down drive transistor coupled to the first and second pull-up drive transistors in series to drive the power switching transistor. When control signal is at a high level, the first pull-up driver is turned on, and the first pull-down driver is turned off. The second pull-up drive transistor being in turn-on or turn-off state is determined by comparing voltage of the power supply with the threshold value. When voltage of the power supply is lower than the threshold value, the first and second pull-up drive transistor are driven together. When voltage of the power supply is higher than the threshold value, the second pull-up driving transistor is turned on only after the driving output is slightly larger than the Miller plateau voltage.

In a gate driver, a comparator input is adapted to be coupled through a resistor and a diode to a first transistor. A latch input is coupled to a comparator output. A second transistor has a first control terminal and a first output terminal. The first output terminal is adapted to be coupled to a control terminal of the first transistor. A third transistor is smaller than the second transistor. The third transistor has a second control terminal and a second output terminal. The second output terminal is adapted to be coupled to the control terminal of the first transistor. Control logic has a logic input and first and second logic outputs. The logic input is coupled to a latch output. The first logic output is coupled to the first control terminal. The second logic output is coupled to the second control terminal.

In general, according to one embodiment, a switch circuit includes first to fourth transistors and first to second resistors. The third transistor includes one terminal coupled to one terminal of the first transistor and another terminal coupled to a control terminal of the first transistor. The fourth transistor includes one terminal coupled to a control terminal of the third transistor, another terminal coupled to another terminal of the first transistor, and a control terminal coupled to the control terminal of the first transistor. The second resistor is coupled between the one terminal of the third transistor and the control terminal of the third transistor.

A transistor control circuit is disclosed. In an embodiment a method includes simultaneously controlling several transistors by a first signal and separately controlling the transistors by distinct second pulsed signals.

Adaptive gate drivers and related methods and systems are disclosed. An example gate driver system includes a comparator, a latch having first and second inputs and outputs, the first input coupled to the comparator, a timer having an input and an output, the input coupled to the first output of the latch, the output coupled to the second input of the latch, control logic having an input and first and second outputs, the input coupled to the second output of the latch, first and second transistors having a gate, a first buffer having an input and an output, the input coupled to the first output of the control logic, the output coupled to the gate of the first transistor, and a second buffer having an input and an output, the input coupled to the second output of the control logic, the output coupled to the gate of the second transistor.

A circuit includes a first power node configured to carry a first voltage having a first voltage level, a second power node configured to carry a second voltage having a second voltage level, an output node, and first and second cascode transistors coupled between the first power node and the output node and to each other at a node. A bias circuit uses the first and second cascode transistors to generate an output signal at the output node that transitions between the first voltage level and a third voltage level, and a delay circuit generates a transition in a first signal from one of the first or second voltage levels to the other of the first or second voltage levels, the transition having a time delay based on the output signal. A contending transistor couples the node to the second power node responsive to the first signal.

A circuit includes a first power node configured to carry a first voltage having a first voltage level, an output node, a node coupled between the first power node and the output node, and a contending transistor coupled between the node and a second power node configured to carry a second voltage having a second voltage level. The circuit generates a signal at the output node that ranges between the first voltage level and a third voltage level, the contending transistor couples the node with the second power node responsive to the signal, a difference between the first voltage level and the second voltage level has a first magnitude, a difference between the first voltage level and the third voltage level has a second magnitude, and the second magnitude is a multiple of the first magnitude having a value greater than one.

A power-switch-system (PSS) having a low-side transistor (LSS) and a high-side transistor (HSS), which are switchable to be conductive or switched to be blocking in respectively alternating time-segments of a switching-period of the PSS. A source-terminal of the LSS is connected to a load-terminal, and a drain-terminal of the LSS is connected to a supply-voltage via a storage-inductor. A drain-terminal of the HSS is connected to the load-terminal, and a source-terminal of the HSS is connected to the supply-voltage via the storage-inductor. Provided is a PSS of this kind, the LSS having at least two transistor-segments. At least two of the transistor-segments have a different electrical resistance in the connection to the storage-inductor. The PSS provides that at least two of the transistor-segments are switched at a different point in time during a switching operation of the PSS to reduce unwanted voltage fluctuations, without markedly increasing switching losses.