A power converter includes a high side device, a low side device connected to the high side device at a switch node, an inductor connected to the high side device and the low side device at the switch node, and a high side driver. The high side driver is configured to drive a gate of the high side device at a first current for a first period of time. In response to the first period of time ending, the high side driver is configured to step down the first current for a second period of time. In response to the second period of time ending, the high side driver is configured to drive the gate of the high side device at the first current.

A power conversion device includes two lower arm switching elements connected in parallel to each other and a lower arm driver circuit that drives the two lower arm switching elements. The two lower arm switching elements respectively include gate terminals and detection terminals used to detect counter-electromotive forces. The power conversion device includes a common connection line that connects the two detection terminals to each other and connects the two detection terminals to an addition circuit of the lower arm driver circuit. A combined electromotive force is transmitted via the common connection line.

An electronic circuit is disclosed. The electronic circuit includes: a half-bridge with a first transistor device (1) and a second transistor device (1a); a first biasing circuit (3) connected in parallel with a load path of the first transistor device (1) and comprising a first electronic switch (31); a second biasing circuit (3a) connected in parallel with a load path of the second transistor device (1a) and comprising a second electronic switch (31a); and a drive circuit arrangement (DRVC). The drive circuit arrangement (DRVC) is configured to receive a first half-bridge input signal (Sin) and a second half-bridge input signal (Sina), drive the first transistor device (1) and the second electronic switch (31a) based on the first half-bridge input signal (Sin), and drive the second transistor device (1a) and the first electronic switch (31) based on the second half-bridge input signal (Sina).

An integrated circuit may be provided with power switching circuitry. The power switching circuitry may include a primary power switch and multiple auxiliary power switches. A power gating control circuit may output control signals for selectively activating the primary power switch and at least one of the auxiliary power switches to charge a gated voltage. One or more voltage detectors may be configured to monitor the gated voltage and to activate the remaining auxiliary power switches in response to detecting that the gated voltage exceeds one or more thresholds. Configured and operated in this way, inrush current surge protection can be achieved while charging up the gated voltage sufficiently fast.

A sense voltage obtained by feeding a sense current of an IGBT into a sense resistor is input to a comparator, and as the reference voltage of the comparator, a sense voltage immediately before the IGBT is turned off is held by a sample and hold circuit for each switching, and is then divided by a voltage dividing circuit and the divided voltage is input to the comparator. The comparator compares the sense voltage with the voltage based on the sense voltage immediately before the IGBT is turned off, and therefore the comparator may accurately detect the falling edge time of the sense voltage and is used for the control for dissolving the imbalance in current with respect to the other IGBTs connected in parallel.

In accordance with an embodiment, a method of operating a switching transistor includes turning-off the switching transistor by transferring charge from a gate-drain capacitance of the switching transistor to a charge storage device, and turning-on the switching transistor by transferring charge from the charge storage device to a gate of the switching transistor. Turning off the switching transistor includes hard-switching and turning-on the switching transistor includes soft-switching.

An extinguishing branch (28) for an electrical circuit (32) includes: a snubber circuit (36) including an energy storage limb (40), wherein the energy storage limb (40) includes first and second energy storage limb portions separated by a first junction (46) to define a first voltage divider, and each energy storage limb portion includes at least one energy storage device (48,50); and an arrester limb (38) connected across the energy storage limb (40), wherein the arrester limb (38) includes first and second arrester limb portions separated by a second junction (52) to define a second voltage divider, and each arrester limb portion includes at least one arrester element (54,56), wherein the first and second junctions (46,52) are connected to define a voltage divider bridge, and the voltage divider bridge is electrically coupleable to the electrical circuit (32) so as to provide, in use, a driving voltage to drive the electrical circuit (32).

A sense voltage obtained by feeding a sense current of an IGBT into a sense resistor is input to a comparator, and as the reference voltage of the comparator, a sense voltage immediately before the IGBT is turned off is held by a sample and hold circuit for each switching, and is then divided by a voltage dividing circuit and the divided voltage is input to the comparator. The comparator compares the sense voltage with the voltage based on the sense voltage immediately before the IGBT is turned off, and therefore the comparator may accurately detect the falling edge time of the sense voltage and is used for the control for dissolving the imbalance in current with respect to the other IGBTs connected in parallel.

A solid state power controller including: a plurality of pairs of FETs connected in parallel, each pair comprising a first, forward-facing FET and a second, backward-facing FET connected by their respective sources; gate drive means for switching said FETs on and off; and means for isolating the sources of the backwards-facing FETs of the plurality of pairs of FETs from each other and operating the backwards-facing FETs in 3.sup.rd quadrant operation mode.

In accordance with an embodiment, a method of operating a switching transistor includes turning-off the switching transistor by transferring charge from a gate-drain capacitance of the switching transistor to a charge storage device, and turning-on the switching transistor by transferring charge from the charge storage device to a gate of the switching transistor. Turning off the switching transistor includes hard-switching and turning-on the switching transistor includes soft-switching.