H03K17/6874

RF switch stack with charge redistribution
11601126 · 2023-03-07 · ·

Methods and devices to address body leakage current generation and bias voltage distribution associated with body leakage current in an OFF state of a FET switch stack are disclosed. The devices include charge redistribution arrangements and bridge networks to perform coupling/decoupling to/from the FET switch stack. Detailed structures of such bridge networks are also described.

MOTOR POWER SUPPLY DEVICE

A motor power supply device includes a first power supply, a motor driven by a power supplied from the first power supply, a first power supply line, a first power supply side semiconductor switch, a first output side semiconductor switch, a first power supply side voltage detection unit disposed on a first power supply side with respect to the first power supply side semiconductor switch on the first power supply line and configured to detect a voltage of the first power supply line, and a control unit configured to execute control to determine a state of power supply from the first power supply to the first power supply side semiconductor switch based on a measured value obtained by the first power supply side voltage detection unit.

Switch driver powering circuit

An assembly for powering a first circuit, including at least one ferrite bead in series with a diode between a first terminal of application of a first voltage and a first terminal of said first circuit.

Electronic switch having an in-line power supply

A two-wire smart load control device, such as an electronic switch, for controlling the power delivered from a power source to an electrical load comprises a relay for conducting a load current through the load and an in-line power supply coupled in series with the relay for generating a supply voltage across a capacitor when the relay is conductive. The power supply controls when the capacitor charges asynchronously with respect to the frequency of the source. The capacitor conducts the load current for at least a portion of a line cycle of the source when the relay is conductive. The load control device also comprises a bidirectional semiconductor switch, which is controlled to minimize the inrush current conducted through the relay. The bidirectional semiconductor switch is rendered conductive in response to an over-current condition in the capacitor of the power supply, and the relay is rendered non-conductive in response to an over-temperature condition in the power supply.

SELF-POWERED SOLID STATE RELAY USING DIGITAL ISOLATORS
20220329168 · 2022-10-13 ·

A circuit includes a solid-state relay, a rectifier, and a current transformer-based power supply. The rectifier is adapted to be coupled to the solid-state relay. The rectifier is configured to provide a voltage to an output terminal responsive to the solid-state relay being in an off state. The current transformer-based power supply is coupled to the rectifier and is adapted to be coupled to a transformer. The current transformer-based power supply is configured to provide a voltage to the output terminal responsive to the solid-state relay being in an on state.

Semiconductor device
11606090 · 2023-03-14 · ·

Provided is a semiconductor device comprising a high-side switching device, a low-side switching device, a high-side driver configured to turn on/off the high-side switching device, a low-side driver configured to turn on/off the low-side switching device, a high-side driving external terminal configured to supply a power supply voltage for driving the high-side driver, and a protection circuit section connected to the high-side driving external terminal. The high-side driver may include a reference potential terminal set to a reference potential of the high-side driver. The protection circuit section may be connected between the high-side driving external terminal and the reference potential terminal.

Scheduling commutation behavior changes for a driver

A driver may comprise a first node, a second node, and processing circuitry. The first node is configured to receive a command from controller circuitry. The second node is configured to receive a commutation signal for activating or deactivating a switch. The processing circuitry is configured to determine, based on the received command, an activation setting for an activation characteristic for the switch and a deactivation setting for a deactivation characteristic for the switch and drive the switch based on the commutation signal. To drive the switch, the processing circuitry is configured to change, at a first time, the deactivation characteristic for the switch from a previous deactivation setting to the determined deactivation setting and change, at a second time that is different from the first time, the activation characteristic for the switch from a previous activation setting to the determined activation setting.

Method of controlling a half-bridge circuit

A method of controlling a half-bridge circuit includes receiving an analog feedback signal proportional to an output of the half-bridge circuit, comparing the received analog feedback signal with a threshold value, selecting a digital feedback signal based on a result of the comparing, comparing the digital feedback signal with a digital reference signal to generate a digital error signal, integrating the digital error signal to generate an integration error signal, downscaling the integral error signal to generate a downscaled integration signal, sampling the downscaled integration signal to generate a sampled integration signal, and generating pulsed signals from the sampled integration signal to provide an input to the half-bridge circuit.

Hybrid power devices

A device includes a first switch and a first diode connected in parallel between a midpoint and a first terminal of the hybrid power device, a second switch and a second diode connected in parallel between the midpoint and a second terminal of the hybrid power device, a third switch coupled between the first terminal and the second terminal, and a third diode connected between the first terminal and the second terminal.

Switch linearization with asymmetrical anti-series varactor pair

Described herein are switches with asymmetrical anti-series varactor pairs to improve switching performance. The disclosed switches can include asymmetrical varactor pairs to reduce distortions. The asymmetry in the varactor pairs can be associated with geometry of each varactor in the pair. The disclosed switches can stack both symmetrical and asymmetrical varactor pairs. The disclosed switches with asymmetrical anti-series varactor pairs can be configured to improve both H2 and H3 simultaneously.