A high voltage power block includes a high voltage power transistor; and a switch driver configured to drive a gate of the high voltage power transistor. The high voltage power block is integrated in a programmable logic device (PLD) including a programmable fabric, a signal wrapper configured to provide signals between the high voltage power transistor and the programmable fabric, and a plurality of internal components. The plurality of internal components integrated in the PLD are programmably connected and characteristics of the high voltage power transistor are programmably adjusted using the programmable fabric and the signal wrapper.

A method for an FPGA includes programming a RRAM memory array with a first bit pattern, shifting the first bit pattern to a shift register array, employing the first bit pattern in operation of the FPGA, programming a RRAM memory array with a second bit pattern concurrent the employing the bit pattern in operation of the FPGA, shifting the second bit pattern to the shift register array, and employing the second bit pattern in operation of the FPGA.

An integrated circuit according to an embodiment includes: first through third basic tiles, the second basic tile being located between the first basic tile and the third basic tile, each of the basic tiles including a first logic block configured to perform a logical operation and a first switch block, the first switch block including a first switch circuit, the first switch circuit including: two-terminal switch elements arranged in a matrix form; input terminals, each of the input terminals being connected to one of terminals of each of the two-terminal switch elements aligned in the same column; and output terminals, each of the output terminals being connected to the other one of the terminals of each of the two-terminal switch elements aligned in the same row.

An integrated circuit enables the selection of a circuit. According to one implementation, a plurality of redundant circuits provide a predetermined function and a voltage sensor may be coupled to receive a reference voltage. A selection circuit may be coupled to the voltage sensor and the reference voltage, wherein the selection circuit selects one of the plurality of redundant circuits to be implemented in the integrated circuit based upon a detected voltage of the reference voltage of the reference voltage.

A field programmable gate array comprising: plurality of functional blocks at least one of the functional blocks comprising at least one function, at least one of the functions using a parameter, wherein the functional blocks are adapted to perform the at least one function in a calculation phase; a data conveyor comprising a plurality of data slots, wherein each functional block is, in a data transfer phase, adapted to receive input data from one or more predefined first slots and/or to provide output data into one or more predefined second slots; and a configuration circuit adapted to configure the parameter for the at least function using the parameter and to define the one or more first slots and/or the one or more second slots for at least one functional block, wherein the field programmable gate array is adapted to cyclically repeat the data transfer phase and calculation phase.

Generating a unique die identifier for an electronic chip including placing the electronic chip in an identifier generation state, wherein the electronic chip comprises a set of test circuits, wherein each of the set of test circuits is attached to a corresponding component on the electronic chip; obtaining an ordered list of race pairs of the set of test circuits; for each race pair in the ordered list of race pairs of the set of test circuits: selecting the race pair of test circuits; executing a race between the selected race pair; and adding an element to the unique die identifier based on an outcome of the executed race; and returning the electronic chip to an operational state.

A high voltage power block includes a high voltage power transistor; and a switch driver configured to drive a gate of the high voltage power transistor. The high voltage power block is integrated in a programmable logic device (PLD) including a programmable fabric, a signal wrapper configured to provide signals between the high voltage power transistor and the programmable fabric, and a plurality of internal components. The plurality of internal components integrated in the PLD are programmably connected and characteristics of the high voltage power transistor are programmably adjusted using the programmable fabric and the signal wrapper.

Generating a unique die identifier for an electronic chip including placing the electronic chip in an identifier generation state, wherein the electronic chip comprises a set of test circuits, wherein each of the set of test circuits is attached to a corresponding component on the electronic chip; obtaining an ordered list of race pairs of the set of test circuits; for each race pair in the ordered list of race pairs of the set of test circuits: selecting the race pair of test circuits; executing a race between the selected race pair; and adding an element to the unique die identifier based on an outcome of the executed race; and returning the electronic chip to an operational state.

In one or more implementations, a data processing device and a data processing method are disclosed that includes a data communication port configured to transmit and receive data to and from at least one computing device. Further, a replicator is included that is configured to replicate ingress data received from the data communication port to a pattern matcher and a field programmable gate array. The pattern matcher is configured to receive the replicated data directly from the replicator and to generate and transmit a trigger signal to the field programmable gate array. Still further, the field programmable gate array is configured to receive the replicated data from the replicator and the trigger signal from the pattern matcher and to perform bit operations on the replicated data as a function of the trigger signal.

In one or more implementations, a data processing device and a data processing method are disclosed that includes a data communication port configured to transmit and receive data to and from at least one computing device. Further, a replicator is included that is configured to replicate ingress data received from the data communication port to a pattern matcher and a field programmable gate array. The pattern matcher is configured to receive the replicated data directly from the replicator and to generate and transmit a trigger signal to the field programmable gate array. Still further, the field programmable gate array is configured to receive the replicated data from the replicator and the trigger signal from the pattern matcher and to perform bit operations on the replicated data as a function of the trigger signal.