An ADC is disclosed. The ADC includes a SAR logic circuit, a DAC, a comparator, and a voltage generator. The voltage generator includes a first switch connected to the comparator configured to selectively connect a second input terminal of the comparator to a reference voltage, a capacitor connected to the second input terminal of the comparator, and a second switch connected to the capacitor and selectively connected to either of a ground voltage and the reference voltage. The second switch is configured to selectively connect the capacitor to either of the ground voltage and the reference voltage, and the SAR logic circuit is further configured to receive the comparator output voltage, and to generate a digital input word for the DAC based on one or more comparator output voltages received from the comparator.

An offset voltage V.sub.OFST is compensated in a digital to analog (DA) convertor using a switched-capacitor circuit, including an input circuit, a first differential amplifier, and an offset cancel circuit comprising a second differential amplifier, in a sampling period, when the second feedback circuit is short, an output voltage of the first differential amplifier is input to a first end of a first capacitor, the offset cancel circuit feeds back a reference voltage to an inverting input terminal of the second differential amplifier and a second end of the first capacitor from an output of the second differential amplifier, in a holding period, when the second feedback circuit is not short, the offset cancel circuit inputs a differential voltage between the reference voltage and the output voltage of the first differential amplifier into an inverting input terminal of the first differential amplifier via a second capacitor.

An analog-to-digital converter (ADC) device includes capacitor arrays, a successive approximation register (SAR) circuitry, and a switching circuitry. When a first capacitor array of the capacitor arrays samples an input signal in a first phase, a second capacitor array of the capacitor arrays outputs the input signal sampled in a second phase as a sampled input signal. The SAR circuitry performs an analog-to-digital conversion on a combination of the sampled input signal and a residue signal generated in the second phase according to a conversion clock signal, in order to generate a digital output. The switching circuitry includes a first capacitor that stores the residue signal generated in the second phase. The switching circuitry couples the second capacitor array and the first capacitor to an input terminal of the SAR circuitry, in order to provide the combination of the sampled input signal and the residue signal.

Systems and methods are disclosed for Successive Approximation Register Analog-to-Digital Converter (SAR ADC) by coupling an ADC capacitive network coupled to a comparator; and performing binary search using a comparator output using a capacitive DAC calibration process to enhance SAR ADC linearity and performance. In one implementation, the calibration process starts with the least significant bit (LSB) capacitor calibration then proceed to higher bit capacitors until all the capacitors are calibrated. Each capacitor consists of fixed-value base capacitor and value-adjustable capacitor. The capacitor calibration logic is implemented based on the process then incorporated into SAR ADC. ADC performs capacitor calibration first before normal conversion operation. The non-ideal aspect of normal conversion operation is preserved and accounted during capacitor calibration. By employing capacitor calibration, the DAC capacitor value can be minimal to enhance settling and conversion rate, SAR ADC performance is improved.

Capacitor structures with pitch-matched capacitor unit cells are described. In an embodiment, the capacitor unit cells are formed by interdigitated finger electrodes. The finger electrodes may be pitch-matched in multiple metal layers within a capacitor unit cell, and the finger electrodes may be pitch-matched among an array of capacitor unit cells. Additionally, border unit cells may be pitch-matched with the capacitor unit cells.

Processing circuitry comprising: a reference node for connection to a reference voltage source so as to establish a local reference voltage signal at the reference node; a signal processing unit connected to the reference node and operable to process an input signal using the local reference voltage signal, wherein the signal processing unit is configured to draw a current from the reference node at least a portion of which is dependent on the input signal; and a current-compensation unit connected to the reference node and operable to apply a compensation current to the reference node, wherein the current-compensation unit is configured, based on an indicator signal indicative of the input signal and/or of the operation of the signal processing unit, to control the compensation current to at least partly compensate for changes in the current drawn from the reference node by the signal processing unit due to the input signal.

Controllable voltage-signal generation circuitry, including: a plurality of segment nodes connected together in series, each adjacent pair of segment nodes connected together via a corresponding coupling capacitor, an end one of the segment nodes serving as an output node; for each of the segment nodes, at least one segment capacitor having a first terminal connected to that segment node and a second terminal connected to a corresponding switch; and switch control circuitry, wherein: each switch is operable to connect the second terminal to one reference voltage source and then instead to another reference voltage source, to apply a voltage change at the second terminal; the reference voltage sources and switches configured such that for each segment node the same voltage change in magnitude is applied by each switch, and such that the voltage change is different in magnitude from the voltage change applied by each switch of another segment node.

Provided is an integrated circuit including an analog-to-digital converter (ADC) configured to convert an analog signal to a digital signal; and a digital signal processor (DSP) configured to process the digital signal, wherein the ADC generates a power source during a process for converting the analog signal into the digital signal and supplies power to the DSP through the power source.

Systems and methods are disclosed for Successive Approximation Register Analog-to-Digital Converter (SAR ADC) by coupling an ADC capacitive network coupled to a comparator; and performing binary search using a comparator output using a capacitive DAC calibration process to enhance SAR ADC linearity and performance. In one implementation, the calibration process starts with the least significant bit (LSB) capacitor calibration then proceed to higher bit capacitors until all the capacitors are calibrated. Each capacitor consists of fixed-value base capacitor and value-adjustable capacitor. The capacitor calibration logic is implemented based on the process then incorporated into SAR ADC. ADC performs capacitor calibration first before normal conversion operation. The non-ideal aspect of normal conversion operation is preserved and accounted during capacitor calibration. By employing capacitor calibration, the DAC capacitor value can be minimal to enhance settling and conversion rate, SAR ADC performance is improved.

A circuit device includes an A/D converter circuit that performs A/D conversion by successive approximation using a charge redistribution type D/A converter circuit having capacitor array circuits on the positive electrode side and the negative electrode side, and quantization error hold circuits that hold charges corresponding to a quantization error in the A/D conversion. The quantization error hold circuits include quantization error hold circuits on the positive electrode side and the negative electrode side having one ends connected to sampling nodes of the capacitor array circuits on the positive electrode side and the negative electrode side. The quantization error hold circuits on the positive electrode side and the negative electrode side are placed on a second direction side orthogonal to a first direction in which the capacitor array circuits on the positive electrode side and the negative electrode side are placed.