A baseband processing unit includes a baseband processor configured to receive a plurality of component carriers of a radio access technology wireless service, and a delta-sigma digitization interface configured to digitize at least one carrier signal of the plurality of component carriers into a digitized bit stream, for transport over a transport medium, by (i) oversampling the at least one carrier signal, (ii) quantizing the oversampled carrier signal into the digitized bit stream using two or fewer quantization bits.

A communication unit (300, 400, 500) is described that includes at least one antenna (302, 402, 502); a plurality of radio frequency (RF) circuits (304, 310, 404, 410) respectively coupled to at least one antenna (302, 402, 502); at least one sigma-delta modulator (316, 416, 616, 816) comprising a number of stages, each stage comprising at least one signal-feedforward coefficient (603, 604, 605), a filter and a feedback gain element, the at least one sigma-delta modulator (316, 416, 616, 816) coupled to the plurality of RF circuits (304, 310, 404, 410) and configured to perform sigma-delta modulation; and a controller (340, 440, 640, 840) operably coupled to the at least one sigma-delta modulator (316, 416, 616, 816). The at least one sigma-delta modulator (316, 416, 616, 816) comprises an input (315, 415, 602, 801, 802, 902) configured to receive multiple multi-phase input signals and the controller (340, 440, 640, 840) is configured to adjust the at least one signal-feedforward coefficient (603, 604, 605) of the at least one sigma-delta modulator (316, 416, 616, 816) when combining the multiple multi-phase input signals.

A semiconductor device includes; a loop filter that receives a differential analog signal and generates a residue signal indicating an error between an analog input signal and an feedback signal, a first ADC that receives the residue signal and generates a first digital representation, a second ADC that receives the analog input signal and generates a second digital representation corresponding to the analog input signal, and a digital to analog converter (DAC) that receives a sum of the first digital representation and the second digital representation and generates the analog feedback signal. At least the first ADC is a multi-bit Successive Approximation Register ADC.

A baseband processing unit includes a baseband processor configured to receive a plurality of component carriers of a radio access technology wireless service, and a delta-sigma digitization interface configured to digitize at least one carrier signal of the plurality of component carriers into a digitized bit stream, for transport over a transport medium, by (i) oversampling the at least one carrier signal, (ii) quantizing the oversampled carrier signal into the digitized bit stream using two or fewer quantization bits.

Proposed is a sigma-delta modulator circuit. The circuit comprises a loopfilter having at least one integrator or resonator section; and a feed-forward path adapted to provide a feed-forward signal to the output of the at least one integrator or resonator section via a filter.

A quantizer includes: a quantizer capacitor having a first end and a second end; an input calculator that receives input voltages, sums the input voltages, and outputs the summed result to the first end of the quantizer capacitor; a scaler that receives reference voltages and a scale code, generates a scale voltage from the reference voltages depending on the scale code, and outputs the scale voltage to the second end of the quantizer capacitor; and a latch that stores an output voltage of the first end of the quantizer capacitor.

A modulator including a delta-sigma modulation circuit having an order greater than 1, and configured to modulate an input signal into a Pulse Density Modulated (PDM) signal; and a Pad Asymmetric Compensation (PAC) circuit configured to linearize a relation between a magnitude of the input signal and a number of rise or fall transitions of the PDM signal by maximizing the number of rise or fall transitions of the PDM signal, and to output a modified PDM signal, wherein the linearized relation is for compensating for any offset in the PDM signal.

An analog-to-digital conversion (ADC) system includes a transconductance amplifier, loop filter, quantizer, logic circuit, and digital-to-analog converter (DAC). The transconductance amplifier is configured to generate a current signal in response to an audio signal. The loop filter is connected to the transconductance amplifier and configured to generate a filtered signal based on the current signal. The quantizer is configured to generate a digital representation of the filtered signal. The logic circuit is configured to generate control signals based on the digital representation. The DAC is coupled to the loop filter's and the transconductance amplifier's output. The DAC includes three-level unit elements, where each unit element is configured to provide one of two signal levels or no signal to the loop filter in response to control signals from the logic circuit. Such an ADC system may allow for a high dynamic range while maintaining low power consumption and low noise.

A multibit flash quantizer circuit, such as included as a portion of delta-sigma conversion circuit, can be operated in a dynamic or configurable manner. Information indicative of at least one of an ADC input slew rate or a prior quantizer output code can be used to establish a flash quantizer conversion window. Within the selected conversion window, comparators in the quantizer circuit can be made active. Comparators outside the conversion window can be made dormant, such as depowered or biased to save power. An output from such dormant converters can be preloaded and latched. In this manner, full resolution is available without requiring that all comparator circuits within the quantizer remain active at all times.

Shortening any of the operational phases of a noise-shaping successive approximation register (SAR) analog-to-digital converter (ADC), including the acquisition phase, the bit trial phase, and the residue charge transfer phase, can result in higher power, and it can be difficult to achieve high speed at low power.

Using various techniques described, the acquisition, bit-trial, and residue charge transfer phases of two or more digital-to-analog converter (DAC) circuits of an ADC circuit can be time-interleaved. The use of two or more DAC circuits can increase or maximize the time available for the acquisition, bit-trial, and residue charge transfer phases.