A communication system includes a processor and a memory that stores recovery bits of a previous message and instructions. The instructions cause the processor to, in response to receiving a new message, obtain the recovery bits of the previous message and selectively generate a candidate message by attempting recovery of the previous message from the new message and the recovery bits of the previous message. The instructions include, in response to an indicator indicating that the recovery was successful, computing a delta between the new message and the candidate message and generating a delivery message based on (i) the computed delta or, in response to the indicator indicating that the recovery was unsuccessful, (ii) the new message. The instructions include calculating new recovery bits from the new message, replacing the stored recovery bits of the previous message with the new recovery bits, and transmitting the delivery message to a destination.

According to one general aspect, an apparatus may include a storage element configured to store both data and metadata, wherein each piece of data is associated with and stored with a corresponding piece of metadata. The apparatus may include a controller processor. The controller processor may be configured to, in response to a piece of data being written to the apparatus: generate a piece of metadata that includes a set of parameters to facilitate a at least partial repair of a block information map, and embed the piece of metadata with the corresponding piece of data.

Disclosed are devices, systems and methods for reducing the latency of a quasi-cyclic linear code decoder. An example method includes receiving a noisy codeword, the codeword having been generated from a quasi-cyclic linear code and provided to a communication channel prior to reception by the decoder; computing a syndrome based on the noisy codeword; generating a plurality of memory cell addresses, a first memory cell address being a function of the syndrome and subsequent memory cell addresses being within a predetermined address range of the function of the syndrome; reading, in a parallel manner to reduce the latency of the decoder, a plurality of error patterns from the plurality of memory cell addresses and computing a checksum for each of the plurality of error patterns; and determining, based on the checksum for each of the plurality of error patterns, a candidate version of the transmitted codeword.

A communication system includes a processor and a memory that stores recovery bits of a previous message and instructions. The instructions cause the processor to, in response to receiving a new message, obtain the recovery bits of the previous message and selectively generate a candidate message by attempting recovery of the previous message from the new message and the recovery bits of the previous message. The instructions include, in response to an indicator indicating that the recovery was successful, computing a delta between the new message and the candidate message and generating a delivery message based on (i) the computed delta or, in response to the indicator indicating that the recovery was unsuccessful, (ii) the new message. The instructions include calculating new recovery bits from the new message, replacing the stored recovery bits of the previous message with the new recovery bits, and transmitting the delivery message to a destination.

In one example in accordance with the present disclosure, a method may include receiving a digit sequence including a subset of N digits encoded with semantic information and determining a set of possible combinations for the N digits in the subset. The method may also include establishing a mapping between each possible combination in the set of possible combinations and a corresponding integer sequence belonging to a set of integer sequences. Each integer sequence in the set of integer sequences is of the length of N1. The method may also include identifying a selected integer sequence corresponding to the subset and replacing n1 digits from the subset with the selected integer sequence. The method may also include replacing a digit of the subset with a digit value calculated to produce a valid checksum for the entire first digit sequence, wherein the first digit is not included in the n1 digits.

A DMA (Direct Memory Access) transfer apparatus acquires information including a transfer source address and a transfer destination address based on a received transfer instruction, selects whether to perform first checksum calculation for data from an area of a memory corresponding to the transfer source address or perform second checksum calculation different from the first checksum calculation, and transfers data obtained via the checksum calculation selected in the selecting to an area of the memory corresponding to the transfer destination address.

A method includes generating an extended result from a first operation circuitry having a result register bit width greater than a bus width associated with a residue check path of a second operation circuitry associated with a floating point unit. An extended result residue less a first portion residue of the extended result received from the residue check path is stored as a first partial result residue. The first partial result residue is compared with a first result residue of the second operation circuitry. The extended result residue less both the first partial result residue and a second portion residue of the extended result received from the residue check path as a second partial result residue is compared with a second result residue of the second operation circuitry.

A network data prediction method applied to a device that implements an OSI model is provided. The device communicates with a target network device that implements the OSI model. The method includes the following steps: generating a transmission data according to a communication protocol of a first abstraction layer, the transmission data being able to be processed by a first peer abstraction layer of the target network device, and the first peer abstraction layer corresponding to the first abstraction layer and obeying the communication protocol; generating a predicted data according to the communication protocol and the transmission data; and transmitting the transmission data and the predicted data to a second abstraction layer.

A verification code generation method is performed in an electronic device which is for performing encoding to generate a video/audio stream having multiple data segments. The verification code generation method includes the following steps. Each time one of the data segments is generated by the encoding, a first-level checksum associated with the data segment is generated, and the first-level checksum is recorded in an accompanying verification file. At an interval of every N data segments of the data segments, a second-level checksum is generated for W consecutive first-level checksums, and the second-level checksum is recorded in the accompanying verification file, such that a subsequent verification method can quickly verify integrity of a part of data according to the accompanying verification file. Wherein, W is a positive integer greater than or equal to 2, N is a positive integer greater than 0 and smaller or equal to W.

A DMA (Direct Memory Access) transfer apparatus acquires information including a transfer source address and a transfer destination address based on a received transfer instruction, selects whether to perform first checksum calculation for data from an area of a memory corresponding to the transfer source address or perform second checksum calculation different from the first checksum calculation, and transfers data obtained via the checksum calculation selected in the selecting to an area of the memory corresponding to the transfer destination address.