This application discloses a retransmitted data sending method, a retransmitted data receiving method, and a related apparatus, and relates to the field of communications technologies. In this solution, a transmit end generates a retransmitted codeword based on information bits of each codeword corresponding to an incorrect MPDU, where the retransmitted codeword includes a codeword having some of information bits included in the incorrect MPDU. For the codeword having some of information bits included in the incorrect MPDU, the transmit end punctures a correctly received information bit in the codeword, and then sends the information bit. In this way, a receive end may directly perform combined decoding or joint decoding on an LLR of a codeword of a retransmitted MPDU and an LLR of a codeword of an MPDU that is incorrectly received last time. This improves transmission efficiency and transmission reliability.

Efficient data path architecture for flash devices requiring multi-pass programming utilizes an external memory as an intermediate buffer to store the encoded data used for a first pass programming of the flash device. The stored encoded data can be read from the external memory for subsequent passes programming instead of fetching the data from an on-chip memory, which stores the data received from a host system. Thus, the on-chip memory can be made available to speed up the next data transfer from the host system.

A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 16200 and a code rate of 4/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 64-symbol mapping.

In a transmitting device, in interchanging to interchange a code bit of an LDPC code in which a code length is 16200 bits and an encoding rate is 8/15 with a symbol bit of a symbol corresponding to any of 8 signal points defined by 8PSK, when 3 bits of code bits stored in three units of storages having a storage capacity of 16200/3 bits and read bit by bit from the units of storages are allocated to one symbol, a bit b0, a bit b1, and a bit b2 are interchanged with a bit y1, a bit y0, and a bit y2, respectively. A position of the interchanged code bit obtained from data transmitted from the transmitting device is returned to an original position. The present technology is applicable to a case of transmitting data using an LDPC code, for example.

The present invention provides a method for accessing a flash memory module, wherein the flash memory module comprises at least one flash memory chip, each flash memory chip comprises a plurality of blocks, each block comprises a plurality of pages, and the method includes the steps of: sending a read command to the flash memory module to ask for data on at least one memory unit; receiving multi-bit information of a plurality of memory cells of the at least one memory unit from the flash memory module; and analyzing the multi-bit information of the plurality of memory cells to obtain a threshold voltage distribution of the plurality of memory cells for determining a decoding process.

Provided is a BCH decoder in which a folded multiplier is equipped. The BCH decoder may include a key equation solver including a plurality of multipliers. The multiplier includes a plurality of calculation blocks configured to perform a calculation operation. Each of the calculation blocks repeatedly performs a calculation operation of a calculation stage for a plurality of calculation stages, outputs one output value on the basis of at least one input value in each calculation stage, and is connected to at least one another calculation block to transfer an output value of a current calculation stage as an input value of the at least one another calculation block in a next calculation stage.

A receiver is provided. The receiver includes: a first decoder configured to decode a superposition-coded signal by using a parity check matrix to generate Low Density Parity Check (LDPC) information word bits and first parity bits corresponding to a first layer signal; an encoder configured to encode the LDPC information word bits and the first parity bits to generate second parity bits, or encode the LDPC information word bits to generate the first parity bits and the second parity bits, by using the parity check matrix; and a second decoder configured to decode a signal which is generated by removing the first layer signal, corresponding to the LDPC information word bits, the first parity bits, and the second parity bits, from the superposition-coded signal, to reconstruct bits transmitted through the second layer signal.

The digital signal processor includes a DRAM including multiple memory cells configured to store data in a parasitic capacitor and a core logic configured to perform an operation of recording, reading, or updating data in the DRAM on the basis of a predetermined digital signal processing architecture. The core logic: records input data in a memory cell of the DRAM; reads the recorded input data before a retention time passes; and externally outputs the data or stores the data in another memory cell of the DRAM.

System and methods described herein includes a method for iterative decoding. The method includes instantiating an iterative decoding procedure to decode a codeword. At each iteration of the iterative decoding procedure, the method further includes retrieving information relating to a plurality of current decoding variables at a current iteration, determining a first current decoding variable to be skipped for the current iteration based on the information, and processing a second decoding variable without processing the first decoding variable to update related decoding variables from the plurality of current decoding variables.

A controller is configured to access information to generate data blocks. The controller includes a data block interleaver and a low-density parity check (LDPC) decoder. The data block interleaver is configured to interleave the data blocks to generate interleaved data blocks. The LDPC decoder is configured to decode the interleaved data blocks.