Patent classifications
H03M13/1191
Using parity data for concurrent data authentication, correction, compression, and encryption
A system for software error-correcting code (ECC) protection or compression of original data using ECC data in a first memory is provided. The system includes a processing core for executing computer instructions and accessing data from a main memory, and a non-volatile storage medium for storing the computer instructions. The software ECC protection or compression includes: a data matrix for holding the original data in the first memory; a check matrix for holding the ECC data in the first memory; an encoding matrix for holding first factors in the main memory, the first factors being for encoding the original data into the ECC data; and a thread for executing on the processing core. The thread includes a Galois Field multiplier for multiplying entries of the data matrix by an entry of the encoding matrix, and a sequencer for ordering operations using the Galois Field multiplier to generate the ECC data.
Accelerated erasure coding system and method
An accelerated erasure coding system includes a processing core for executing computer instructions and accessing data from a main memory, and a non-volatile storage medium for storing the computer instructions. The processing core, storage medium, and computer instructions are configured to implement an erasure coding system, which includes: a data matrix for holding original data in the main memory; a check matrix for holding check data in the main memory; an encoding matrix for holding first factors in the main memory, the first factors being for encoding the original data into the check data; and a thread for executing on the processing core. The thread includes: a parallel multiplier for concurrently multiplying multiple entries of the data matrix by a single entry of the encoding matrix; and a first sequencer for ordering operations through the data matrix and the encoding matrix using the parallel multiplier to generate the check data.
MEMORY, MEMORY MODULE, MEMORY SYSTEM, AND OPERATION METHOD OF MEMORY SYSTEM
A memory system may include an error correction code generation circuit configured to generate a first error correction code having a large bit number by using write data and a first H matrix in a first error correction mode, and to generate a second error correction code having a small bit number by using the write data and a second H matrix in a second error correction mode, and a memory core configured to store the first error correction code and the write data in the first error correction mode, and to store the second error correction code and the write data in the second error correction mode.
APPARATUS AND METHOD FOR DECODING POLAR CODES
The present disclosure relates to a method and an apparatus for decoding polar codes and the polar code decoding method according to an exemplary embodiment of the present disclosure is a polar code decoding method performed by a polar code decoding apparatus which includes receiving a code word vector generated by polar encoding; and decoding the code word vector based on a soft cancellation (SCAN) decoding method and a round-trip belief propagation (BP) decoding method, in the decoding, an inner code of the code word vector may be decoded by the round-trip belief propagation method and an outer code may be decoded by the SCAN decoding method.
SPARSE-CODED AMBIENT BACKSCATTER COMMUNICATION METHOD AND SYSTEM
The present disclosure relates to a sparse-coded ambient backscatter communication method and a system. According to the sparse-coded ambient backscatter communication method, in an ambient backscatter system including an access point and a plurality of sensor nodes, each sensor node transmits a code word in a non-orthogonal multiple access (NOMA) manner using sparsity of a signal by a duty cycling operation and the access point detects a superimposed signal transmitted in the NOMA manner by an iterative decoding method in which a dyadic channel and intersymbol interference are reflected. The present disclosure may reduce the implementation cost by reducing the number of impedances required to modulate data of a batteryless sensor node in an Internet of Things environment and utilize the dyadic backscatter channel to detect a signal, thereby providing massive connectivity of the access point.
Systems and methods for advanced iterative decoding and channel estimation of concatenated coding systems
Systems and methods for decoding block and concatenated codes are provided. These include advanced iterative decoding techniques based on belief propagation algorithms, with particular advantages when applied to codes having higher density parity check matrices such as iterative soft-input soft-output and list decoding of convolutional codes, Reed-Solomon codes and BCH codes. Improvements are also provided for performing channel state information estimation including the use of optimum filter lengths based on channel selectivity and adaptive decision-directed channel estimation. These improvements enhance the performance of various communication systems and consumer electronics. Particular improvements are also provided for decoding HD radio signals, satellite radio signals, digital audio broadcasting (DAB) signals, digital audio broadcasting plus (DAB+) signals, digital video broadcasting-handheld (DVB-H) signals, digital video broadcasting-terrestrial (DVB-T) signals, world space system signals, terrestrial-digital multimedia broadcasting (T-DMB) signals, and China mobile multimedia broadcasting (CMMB) signals. These and other improvements enhance the decoding of different digital signals.
Message passing algorithm decoder and methods
Methods and devices are disclosed for receiving and detecting sparse data sequences using a message passing algorithm (MPA) with early propagation of belief messages. Such data sequences may be used in wireless communications systems supporting multiple access, such as sparse code multiple access (SCMA) systems. The determination and passing of one or more messages for an edge between a function node and a variable node in a factor graph representation of the system may be performed in serial with determined values available early for subsequent computations. The serial computations may be scheduled based on various factors.
Soft Output Decoding of Polar Codes
According to certain embodiments, a method is provided for generating soft information for code bits of polar codes. The method includes receiving, by a decoder of a receiver, soft information associated with coded bits from a first module of the receiver and using a tree structure of the polar code to generate updated soft information. The updated soft information is output by the decoder for use by a second module of the receiver.
Mutual-information based recursive polar code construction
Decoding and encoding methods, systems, and devices for wireless communication are described. One method may include receiving a codeword over a wireless channel, the codeword being encoded using a polar code, identifying a set of repeated bit locations in the received codeword, and identifying a set of bit locations of the polar code used for information bits for the encoding. The set of bit locations may be determined based at least in part on recursively partitioning bit-channels of the polar code for each stage of polarization and assigning portions of a number of the information bits to bit-channel partitions of each stage of polarization based on a mutual information transfer function of respective aggregate capacities of the bit-channel partitions. The method may also include decoding the received codeword according to the polar code to obtain an information bit vector at the set of bit locations, and other aspects and features.
POLAR-CODE BASED ENCODER AND METHOD FOR CONFIGURING DIVIDE AND CONQUER STRUCTURE OF POLAR-CODE BASED ENCODER
A polar-code based encoder is used to perform a transfer of useful data to a polar-code based decoder via a Binary Discrete-input Memory-less Channel. The Divide and Conquer structure consists of a multiplexer having useful data bits and a set of frozen bits as inputs followed by a polarization block of size N=2.sup.L, wherein the polarization block of size N comprises a set of front kernels followed by a shuffler and two complementary polarization sub-blocks of size N/2 with a similar structure as the polarization block of size N but with half its size. A dynamically configurable interleaver is present between the shuffler and one and/or the other of the complementary polarization sub-blocks at each recursion of the Divide and Conquer structure. The configuration of the dynamically configurable interleavers is dynamically modified according to changes detected in the Binary Discrete-input Memory-less Channel.