A data decoder includes a communication unit receiving a bit signal with encoded data; a first operation unit that bit shifts the bit signal by a first length, corresponding to a length of a spreading code used to encode the data, to generate a first operation stream; a second operation unit generating a second operation stream without the spreading code; a third operation unit that bit shifts the second operation stream by a second length to generate a third operation stream; a fourth operation unit generating a fourth operation stream from which the data is removed using the second operation stream and the third operation stream; and a polynomial generator that decodes the encoded data using the fourth operation stream.

An error correction and fault tolerance method and system for an array of disks is presented. The array comprises k+5 disks, where k disks store user data and 5 disks store computed parity. The present invention further comprises a method and a system for reconstituting the original content of each of the k+5 disks, when up to 5 disks have been lost, wherein the number of disks at unknown locations is E and the number of disks wherein the location of the disks is known is Z. All combinations of faulty disks wherein Z+2×E≤4 are reconstituted. Some combinations of faulty disks wherein Z+2×E≥5 are either reconstituted, or errors are limited to a small list.

A semiconductor device includes a selection input circuit and a core data generation circuit. The selection input circuit is configured to generate selection data, a selection parity, and a selection data control signal from data, a parity, and a data control signal during a write operation and sets the selection data, the selection parity, and the selection data control signal to a predetermined logic level during a pattern write operation. The core data generation circuit is configured to receive drive data, a drive parity, and a drive data control signal driven by the selection data, the selection parity, and the selection data control signal to generate core data which are stored into a memory core according to whether an error correction operation and a data inversion operation is performed.

Provided are a data processing method and device. The data processing method includes: performing Polar code encoding on an input bit sequence having a length of K bits to obtain an encoded bit sequence having a length of N bits, and determining a bit sequence to be transmitted from the encoded bit sequence according to a data characteristic of an information bit sequence and a predetermined rate matching scheme. K is a positive integer and N is a positive integer greater than or equal to K.

The data decoding apparatus includes a communication unit receiving a bit signal with encoded data; a first operation unit performing a bit shift on the bit signal by a first length corresponding to a length of a spreading code used to encode the data to generate a first operation stream; a second operation unit generating a second operation stream from which the spreading code is removed using the bit signal and the first operation stream; a third operation unit performing a bit shift on the second operation stream by a second length to generate a third operation stream; a fourth operation unit generating a fourth operation stream from which the data is removed using the second operation stream and the third operation stream; and a polynomial generator generating a generator polynomial capable of decoding the data encoded using the fourth operation stream.

Memory controllers, devices and associated methods are disclosed. In one embodiment, a memory controller includes write circuitry to transmit write data to a memory device, the write circuitry includes a write error detection correction (EDC) encoder to generate first error information associated with the write data. Data bus inversion (DBI) circuitry conditionally inverts data bits associated with each of the write data words based on threshold criteria. Read circuitry receives read data from the memory device. The read circuitry includes a read EDC encoder to generate second error information associated with the received read data. Logic evaluates the first and second error information and conditionally reverse-inverts at least a portion of the read data based on the decoding.

An erroneous bit determining circuit and a method are provided. The method includes: respectively performing a Hamming operation for an information symbol having an even weight and an information symbol having an odd weight to acquire a check symbol configured for the information symbol having an even weight and a check symbol configured for the information symbol having an odd weight; and respectively generating corresponding code words based on the information symbol having an even weight, the information symbol having an odd weight and the check symbols configured therefor. In this way, information symbols having the same number of bits are corrected without increasing the number of check symbol bits, and thus symbol transmission rate is improved.

An error correction and fault, tolerance method and system for an array of disks is presented. The array comprises k+5 disks, where k disks store user data and 5 disks store computed parity. The present invention further comprises a method and a system for reconstituting the original content of each of the k+5 disks, when up to disks have been lost, wherein the number of disks at unknown locations is E and the number of disks wherein the location of the disks is known is Z. All combinations of faulty disks wherein Z+2×E≤4 are reconstituted. Some combinations of faulty disks wherein Z+2×E≤5 are either reconstituted, or errors are limited to a small list.

An apparatus comprises an input register comprising a state register and a parity field, a first round secure hash algorithm (SHA) datapath communicatively coupled to the state register, comprising a first section to perform a step of a SHA calculation, a second section to perform a step and a step of the SHA calculation, a third section to perform a step of the SHA calculation and a fourth section to perform a step of the SHA calculation.

An error correction code (ECC) decoder includes a syndrome calculation block and a path controller. The syndrome calculation block is configured to perform a syndrome calculation for generating a syndrome from a codeword. The path controller is configured to output data transmitted through first to third paths. The first path is a path for transmitting the codeword to the path controller when no error is detected. The second path includes a single-error decoding logic circuit, and the single-error decoding logic circuit corrects a single error of the codeword to transmit the corrected codeword to the path controller through the second path. The third path includes a multi-error decoding logic circuit, and the multi-error decoding logic circuit corrects at least two errors of the codeword to transmit the corrected codeword to the path controller.