H03M13/151

Techniques of additional bit freezing for polar codes with rate matching
10903938 · 2021-01-26 · ·

In an aspect of the disclosure, a method, a computer-readable medium, and wireless equipment are provided. The wireless equipment obtains an integer E and an integer N. E encoded bits are to be selected for transmission from N encoded bits output from an encoder. The wireless equipment determines F inputs from N inputs of the encoder based on E and N. The F inputs do not include S inputs that correspond to S outputs of the encoder generating encoded bits not to be transmitted. The wireless equipment sets the F inputs to a predetermined value.

Methods, systems, and computer-readable media for decoding a cyclic code

A method for decoding a cyclic code is disclosed. The method includes: determining a plurality of syndromes for the cyclic code; determining, by a hardware processor, a first coefficient and a second coefficient based on the plurality of syndromes; determining, by the hardware processor, a third coefficient based on the second coefficient; and generating an error-locator polynomial based on the first coefficient, the second coefficient, and the third coefficient.

Accelerated processing for maximum distance separable codes using composite field extensions

Disclosed apparatus and method improve the computational efficiency of encoding and decoding data having erasures according to a maximum distance separable (MDS) code based on a Reed-Solomon code. Thus, n encoded fragments are formed by multiplying k data fragments by an nk generator matrix for the MDS code. The code is formed by reducing, in the generator matrix to the extent possible, the size of the finite field to which entries belongin some cases to the base field having only two elements. In this way, unlike codes known in the art, the generator matrix has more than one column whose entries each take values in the finite field having two elements. In some cases, the generator matrix has a column whose entries each take values in one or more intermediate fields between the finite field having two elements and the encoding field.

GENERATION OF CODED PSEUDORANDOM SEQUENCES
20240014928 · 2024-01-11 ·

Methods, systems, and devices for wireless communication are described. A wireless device may generate a coded pseudorandom using an encoder that implements error detection and/or error correction techniques. A bit sequence of information bits may be segmented into a plurality of bit groups, and each bit group may be mapped to a respective symbol to generate a plurality of ordered information symbols. The plurality of ordered information symbols may be encoded (e.g., by the encoder) to generate a plurality of codewords. Each codeword may be demapped to generate a plurality of sequences that are multiplexed to generate the pseudorandom sequence. A signal that is generated based on the pseudorandom sequence may be transmitted by the wireless device. In some examples, the wireless device may generate a reference signal based on orthogonal or pseudo-orthogonal random sequences generated by applying an orthogonal cover code to a pseudorandom sequence.

Methods, systems and computer-readable media for decoding cyclic code

A method for decoding a (n, k, d) cyclic code is disclosed. The method includes: receiving a word corresponding to the cyclic code; constructing a look-up table, wherein the look-up table includes k syndrome vectors and k error patterns; computing a syndrome vector of the received word by a hardware processor; comparing the weight of the syndrome vector of the received word with an error-correcting capacity; decoding the received word by adding the received word and the syndrome vector if the weight of the syndrome vector of the received word is not more than the error-correcting capacity; decoding the received word by inverting bits in the message section in sequence and re-compute a syndrome vector of the inverted received word if the weight of the syndrome vector of the received word is more than the error-correcting capacity.

Frozen bits based pruning and early termination for polar decoding

Methods, systems, and devices for wireless communication are described. The examples described herein may enable a decoder to determine path metrics for various decoding paths based on identified frozen bit locations of a polar code. The path metric for a decoding path may be based on bit metrics determined for the identified frozen bit locations along the decoding path. Once the path metrics and bit metrics are determined, the decoder may compare these metrics to threshold criteria and determine whether to discard decoding paths based on the comparison. The techniques described herein for discarding decoding paths may allow the decoder to discard, prune, or disqualify certain decoding paths that are unlikely to provide an accurate representation of bits received from another device. Consequently, the decoder may be able to save power by terminating a decoding process early (i.e., early termination) if all paths are discarded, pruned, or disqualified.

Distributed CRC-Assisted Polar Code Construction

According to some embodiments, a method in a wireless device comprises obtaining a set of information bits for wireless transmission and dividing the set of information bits into one or more subsets of information bits. For each subset, generating extra cyclic redundancy check (CRC) bits using a CRC polynomial capable of generating N CRC bits. The extra CRC bits for each subset comprise less than N CRC bits. The method further comprises: generating a final set of N or less CRC bits for the set of information bits using the CRC polynomial; generating a set of coded bits by encoding the set of information bits for wireless transmission, together with the extra CRC bits and the final set of CRC bits, using a polar encoder; and transmitting the set of coded bits using a wireless transmitter.

MEMORY CONTROLLER AND METHOD OF DATA BUS INVERSION USING AN ERROR DETECTION CORRECTION CODE
20200162104 · 2020-05-21 ·

Memory controllers, devices and associated methods are disclosed. In one embodiment, a memory controller includes write circuitry to transmit write data to a memory device, the write circuitry includes a write error detection correction (EDC) encoder to generate first error information associated with the write data. Data bus inversion (DBI) circuitry conditionally inverts data bits associated with each of the write data words based on threshold criteria. Read circuitry receives read data from the memory device. The read circuitry includes a read EDC encoder to generate second error information associated with the received read data. Logic evaluates the first and second error information and conditionally reverse-inverts at least a portion of the read data based on the decoding.

Read-foreign-slices request for improved read efficiency with bundled writes

A method begins by sending a set of read requests to a first set of storage units of the DSN. The method continues by sending a set of read foreign requests to a second set of storage units of the DSN. The method continues by receiving favorable responses to the set of read requests. When a favorable response is received regarding the read foreign request, the method continues by determining whether an encoded data slice (EDS) contained in the favorable response is needed to obtain a decode threshold number of EDSs. When the EDS is needed, the method continues by including the EDSs contained in the favorable response regarding the read foreign request with other EDSs received in the favorable responses to the set of read requests to produce the decode threshold number of EDSs. The method continues by decoding the threshold number of EDSs to recover the data segment.

Decoding apparatus, decoding method and program

To reduce the processing amount of a field multiplication. a denotes a k-th order vector whose elements are a.sub.0, . . . , a.sub.k1 (a.sub.0, . . . , a.sub.k1GF(x.sup.q)). A denotes an n-by-k matrix formed by vertically connecting a identity matrix and a Vandermonde matrix. b denotes an n-th order vector obtained by multiplying the vector a and the matrix A whose elements are b.sub.0, . . . , b.sub.n1 (b.sub.0, . . . , b.sub.n1GF(x.sup.q)). A vector conversion part 11 generates a -th order vector b using elements b.sub.p0, . . . , b.sub.p1 of the vector b. An inverse matrix generation part 12 generates a -by- inverse matrix A.sup.1. A plaintext computation part 13 computes elements a.sub.e0, . . . , a.sub.e1 of the vector a by multiplying the vector b and the inverse matrix A.sup.1.