A memory device that checks an error of a memory cell and a memory module including the same are disclosed. The memory module includes a first memory device and a second memory device. The first memory device includes a first area in which normal data are stored, and a second area in which error check data are stored. The second memory device stores reliability information about the normal data that is stored in the first area of the first memory device. The first memory device outputs a result of comparing the normal data read from the first area of the first memory device to the error check data read from the second area of the first memory device.

An erroneous bit determining circuit and a method are provided. The method includes: respectively performing a Hamming operation for an information symbol having an even weight and an information symbol having an odd weight to acquire a check symbol configured for the information symbol having an even weight and a check symbol configured for the information symbol having an odd weight; and respectively generating corresponding code words based on the information symbol having an even weight, the information symbol having an odd weight and the check symbols configured therefor. In this way, information symbols having the same number of bits are corrected without increasing the number of check symbol bits, and thus symbol transmission rate is improved.

In an aspect of the disclosure, a method, a computer-readable medium, and wireless equipment are provided. The wireless equipment obtains an integer E and an integer N. E encoded bits are to be selected for transmission from N encoded bits output from an encoder. The wireless equipment determines F inputs from N inputs of the encoder based on E and N. The F inputs do not include S inputs that correspond to S outputs of the encoder generating encoded bits not to be transmitted. The wireless equipment sets the F inputs to a predetermined value.

An apparatus for correcting at least one bit error within a coded bit sequence includes an error syndrome generator and a bit error corrector. The error syndrome generator determines the error syndrome of a coded bit sequence derived by a multiplication of a check matrix with a coded bit sequence.

Generally discussed herein are systems, devices, and methods for entwined encryption and error correction and/or error detection. An entwined cryptographic encode device can include a memory including data indicating a set of relatively prime, irreducible polynomials stored and indexed thereon, entwined encryption encoding circuitry to receive data, transform the data to a set of data integers modulo respective polynomial integers representative of respective polynomials of the polynomials stored on the memory, and perform a Da Yen weave on the transformed data based on received cipher data, and provide the weaved transformed data to a medium.

Memory controllers, devices and associated methods are disclosed. In one embodiment, a memory controller includes write circuitry to transmit write data to a memory device, the write circuitry includes a write error detection correction (EDC) encoder to generate first error information associated with the write data. Data bus inversion (DBI) circuitry conditionally inverts data bits associated with each of the write data words based on threshold criteria. Read circuitry receives read data from the memory device. The read circuitry includes a read EDC encoder to generate second error information associated with the received read data. Logic evaluates the first and second error information and conditionally reverse-inverts at least a portion of the read data based on the decoding.

The present disclosure relates to apparatuses and method for encoding using error protection codes. An example apparatus comprises circuitry, for instance, including an encoder configured to compute parity data based, at least in part, on program data and on predetermined coefficient data. The predetermined coefficient data is determined independent of the program data.

A method for decoding a (n, k, d) cyclic code is disclosed. The method includes: receiving a word corresponding to the cyclic code; constructing a look-up table, wherein the look-up table includes k syndrome vectors and k error patterns; computing a syndrome vector of the received word by a hardware processor; comparing the weight of the syndrome vector of the received word with an error-correcting capacity; decoding the received word by adding the received word and the syndrome vector if the weight of the syndrome vector of the received word is not more than the error-correcting capacity; decoding the received word by inverting bits in the message section in sequence and re-compute a syndrome vector of the inverted received word if the weight of the syndrome vector of the received word is more than the error-correcting capacity.

Methods, systems, and devices for wireless communication are described. The examples described herein may enable a decoder to determine path metrics for various decoding paths based on identified frozen bit locations of a polar code. The path metric for a decoding path may be based on bit metrics determined for the identified frozen bit locations along the decoding path. Once the path metrics and bit metrics are determined, the decoder may compare these metrics to threshold criteria and determine whether to discard decoding paths based on the comparison. The techniques described herein for discarding decoding paths may allow the decoder to discard, prune, or disqualify certain decoding paths that are unlikely to provide an accurate representation of bits received from another device. Consequently, the decoder may be able to save power by terminating a decoding process early (i.e., early termination) if all paths are discarded, pruned, or disqualified.

A method for decoding a cyclic code is disclosed. The method includes: determining a plurality of syndromes for the cyclic code; determining, by a hardware processor, a first coefficient and a second coefficient based on the plurality of syndromes; determining, by the hardware processor, a third coefficient based on the second coefficient; and generating an error-locator polynomial based on the first coefficient, the second coefficient, and the third coefficient.