A method includes determining a quantity of errors for a bit string based on a quantity of bits having a logical value of one within the bit string and writing an indication corresponding to the quantity of errors for the bit string to an array of memory cells. The method can further include determining that the quantity of errors for the bit string has reached a threshold quantity of errors and refraining from performing a subsequent operation to determine the quantity of errors for the bit string in response to determining that the quantity of errors for the bit string has reached the threshold quantity of errors.

Systems and methods for Polar encoding with a blockwise checksum are provided. The method involves processing a set of K information blocks to produce a blockwise checksum with u blocks, where K>=2, and u>=1, and where each information block or checksum block contains P bits. The blockwise checksum may, for example, be a Fletcher checksum. The Polar code may be based on an m-fold Kronecker product matrix. Then, an N-bit input vector is produced with PK information bits and the Pu blockwise checksum bits, and with NPKPu frozen bits, where N=2.sup.m where m>=2. The N-bit input vector is processed to produce a result equivalent to multiplying the input vector by a Polar code generator matrix to produce a codeword. The codeword is then transmitted or stored.

A technique to accelerate Galois Field (GF) arithmetic. The technique, which does not rely on any specific processor instruction set, can be used to accelerate erasure coding within storage systems.

Described are methods, systems, and apparatus, including computer program products for error correction coding and decoding procedures for data storage or transfer. A plurality of data blocks is received. A plurality of checksum blocks are generated by multiplying the plurality of data blocks by a coding matrix, where the coding matrix comprises values of at least one basic interpolation polynomial and the multiplying is according to a finite field arithmetic for a finite field comprising all possible values of the plurality of data blocks and the plurality of coding blocks. The plurality of data blocks and the plurality of checksum blocks are stored in a data storage medium.

A method of decoding a biphase mark coded (BMC) data stream. A BMC encoded signal (BMC signal) including a preamble and data payload is received at a receiver which includes a BMC decoder state machine (state machine). The preamble is processed using the state machine including measuring a total duration spanning at least three transitions to provide a 2 UI duration measure, a calculated 0.75 UI duration value (0.75 UI duration value) is generated from the 2 UI duration measure, and the 0.75 UI duration value is compared to a programmed UI range. Provided the 0.75 UI duration value is within the programmed UI range data, respective bits are extracted bit-by-bit from the data payload using the 0.75 UI duration value to obtain unencoded data.

A semiconductor device includes a selection input circuit and a core data generation circuit. The selection input circuit is configured to generate selection data, a selection parity, and a selection data control signal from data, a parity, and a data control signal during a write operation and sets the selection data, the selection parity, and the selection data control signal to a predetermined logic level during a pattern write operation. The core data generation circuit is configured to receive drive data, a drive parity, and a drive data control signal driven by the selection data, the selection parity, and the selection data control signal to generate core data which are stored into a memory core according to whether an error correction operation and a data inversion operation is performed.

A method includes determining a quantity of errors for a bit string based on a quantity of bits having a logical value of one within the bit string and writing an indication corresponding to the quantity of errors for the bit string to an array of memory cells. The method can further include determining that the quantity of errors for the bit string has reached a threshold quantity of errors and refraining from performing a subsequent operation to determine the quantity of errors for the bit string in response to determining that the quantity of errors for the bit string has reached the threshold quantity of errors.

A communication device for uplink transmission with a first type of information and a second type of information includes a demultiplexing circuit, a vector selection circuit, a permutation circuit and a Reed-Muller encoding circuit. The demultiplexing circuit generates a first group of information bits and a second group of information bits according to the first type of information and the second type of information. The vector selection circuit selects code vectors from a predetermined vector set for the first group of information bits and the second group of information bits. The permutation circuit permutes the code vectors according to the first group of information bits and according to the second group of information bits. The Reed-Muller encoding circuit encodes the first group of information bits and the second group of information bits with the permuted code vectors for providing different levels of protection.

A method for operating a memory includes receiving an input data set, saving a first level error correcting code ECC for the data in the input data set, saving second level ECCs for a plurality of second level groups of the data in the data set, storing the data set in the memory, and testing the data set to determine whether to use the first level ECC or the second level ECCs. The method includes, if the first level ECC is used, storing a flag enabling use of the first level ECC, else if the second level ECCs are used, storing a flag enabling use of the second level ECCs. The method includes storing the second level ECCs in a replacement ECC memory, and storing a pointer indicating locations of the second level ECCs in the replacement ECC memory.

Disclosed are methods for reading a set of bits from a NVM array (such as a SPI or parallel NOR NVM or otherwise) including: retrieving each of the set of bits from the NVM array substantially in parallel, applying substantially in parallel to each of the retrieved bits a segmented search, each search indexed using an order number of the respective bit being checked, and correcting a bit whose search indicates an error.