Techniques for implementing a local neural network and global decoding scheme for quantum error correction of circuit-level noise within quantum surface codes such that the decoding schemes have fast decoding throughout and low latency times for quantum algorithms are disclosed. A local neural network decoder may be pre-trained via a supervised learning technique such that the local neural network decoder may be applied for error correction in the presence of circuit-level noise in arbitrarily sized surface codes in a local decoding stage. Prior to a global decoding stage, an intermediate stage may be used to remove vertical pairs of highlighted vertices within the matching graph, which may reduce a syndrome density within the matching graph to allow for faster decoding at the global decoding stage. Such an intermediate stage may include application of a syndrome collapse or vertical cleanup technique.

The present invention is directed to data communication systems and methods thereof. According to various embodiments, the present invention provides a communication with a reconfigurable forward-error-correction (FEC) module. The FEC module processes data received from two or more communication lanes, and depending on the mode of operation, the FEC module can combine data from the two or more communication lanes and perform error correction on the combined data, or the FEC module can processes data from the two communications lanes separately and perform error correction independently for the each of the data communication lanes. There are other embodiments as well.

A method includes calculating a first syndrome of a codeword read from a memory location under a first set of conditions and calculating a second syndrome of the codeword read from the memory location under a second set of conditions. The method also includes analyzing the first and second syndromes and applying one of the first and second syndromes to the codeword to find the codeword having a minimum number of errors.

The present disclosure relates to apparatuses and method for encoding using error protection codes. An example apparatus comprises circuitry, for instance, including an encoder configured to compute parity data based, at least in part, on program data and on predetermined coefficient data. The predetermined coefficient data is determined independent of the program data.

A method and an apparatus for transmitting broadcast signals thereof are disclosed. The apparatus for transmitting broadcast signals, the apparatus comprises an encoder to encode service data corresponding to a number of physical paths, a time interleaver to time interleave the encoded service data in each physical path, a frame builder to build at least one signal frame including the time interleaved service data, a modulator to modulate data in the built at least one signal frame by an OFDM (Orthogonal Frequency Division Multiplex) scheme and a transmitter to transmitting the broadcast signals having the modulated data.

A method for decoding a (n, k, d) cyclic code is disclosed. The method includes: receiving a word corresponding to the cyclic code; constructing a look-up table, wherein the look-up table includes k syndrome vectors and k error patterns; computing a syndrome vector of the received word by a hardware processor; comparing the weight of the syndrome vector of the received word with an error-correcting capacity; decoding the received word by adding the received word and the syndrome vector if the weight of the syndrome vector of the received word is not more than the error-correcting capacity; decoding the received word by inverting bits in the message section in sequence and re-compute a syndrome vector of the inverted received word if the weight of the syndrome vector of the received word is more than the error-correcting capacity.

A method for decoding a cyclic code is disclosed. The method includes: determining a plurality of syndromes for the cyclic code; determining, by a hardware processor, a first coefficient and a second coefficient based on the plurality of syndromes; determining, by the hardware processor, a third coefficient based on the second coefficient; and generating an error-locator polynomial based on the first coefficient, the second coefficient, and the third coefficient.

A storage device syndrome-weight-based error correction system includes a syndrome-weight-based error correction subsystem that is coupled to a storage subsystem in a chassis. The syndrome-weight-based error correction subsystem performs a first error correction hard decoding operation on the storage subsystem that utilizes first read voltage thresholds and that generates a first final codeword candidate having a first syndrome weight. The syndrome-weight-based error correction subsystem then performs error correction hard decoding read voltage threshold real-time search operations to determine second read voltage thresholds, and performs a second error correction hard decoding operation on the storage subsystem that utilizes the second read voltage thresholds and that generates a second final codeword candidate having a second syndrome weight. If the syndrome-weight-based error correction subsystem determines that the first syndrome weight is less than the second syndrome weight, it performs error correction soft decoding operations using the first read voltage thresholds.

A memory includes a first check matrix calculation circuit suitable for generating a first parity by calculating a group indicator portion of a check matrix and a write data; a memory core suitable for storing the write data and the first parity; a first syndrome calculation circuit suitable for generating a first syndrome by adding the first parity which is read from the memory core to a first calculation result obtained by calculating the group indicator portion and the data which is read from the memory core; and a failure determination circuit suitable for accumulating the first syndromes for a region of the memory core to generate a vector and determining a presence of a failure of the region based on the vector.

A method to correct a fault in application of a Clifford circuit to a qubit register of a quantum computer comprises: (A) receiving circuit data defining the Clifford circuit; (B) emitting outcome code based on the circuit data, the outcome code including a series of outcome checks each corresponding to an anticipated error syndrome of the application of the Clifford circuit to the qubit register; and (C) emitting space-time quantum code corresponding to the Clifford circuit based on the circuit data and on the outcome code, the space-time quantum code including a series of check operators that support quantum-error correction, thereby enabling fault correction in the application of the Clifford circuit to the qubit register.