A sensor synchronization system for an autonomous vehicle is described. Upon initializing a master clock on a master processing node for a sensor apparatus of the autonomous vehicle, the system determines whether an external timing signal is available. If the signal is available, the system synchronizes the master clock with the external timing signal. Based on a clock cycle of the master clock, the system propagates timestamp messages to the sensors of the sensor apparatus, receives sensor data, and formats the sensor data based on the timestamp messages.

Embodiments of the present invention relate to a method and a device for providing a clock signal to an application, comprising (a) determining a time difference between a clock device and the clock signal; if the time difference is above a predetermined threshold x, (b) calibrating a first time unit and, during calibrating the first time unit, (c) using a second time unit for providing the clock signal to the application.

Systems, methods, and computer-readable media for authenticating time sources using attestation-based techniques include receiving, at a destination device, a time reference signal from a source device, the source and destination devices being network devices. The time reference signal can include a time synchronization signal or a time distribution signal. The destination device can obtain attestation information from one or more fields of the time reference signal and determine whether the source device is authentic and trustworthy based on the attestation information. The destination device can also determine reliability or freshness of the time reference signal based on the attestation information. The time reference signal can be based on a Network Time Protocol (NTP), a Precision Time Protocol (NTP), or other protocol. The attestation information can include Proof of Integrity based a Canary stamp, a hardware fingerprint, a Secure Unique Device Identification (SUDI) of the source device, or an attestation key.

A phase-locked loop (PLL) performs hitless switching from a first reference clock (ref1) to a second reference clock (ref2) by entering holdover mode (418), and aligning the feedback clock (fbclk) to the second reference clock while in holdover mode. The alignment is performed by adjusting a divisor input (D) for the multi-mode divider (128) that divides the output clock frequency (PLLout) to generate the feedback clock. Other features are also provided.

This application provides a method for sending and receiving a clock synchronization packet in FlexE. The method includes: generating, by a sending apparatus, indication information and a plurality of data blocks, where the plurality of data blocks are obtained by encoding a first clock synchronization packet, the indication information is used to indicate a first data block, and the first data block is a data block used for timestamp sampling in the plurality of data blocks; determining, by the sending apparatus, according to the indication information, a moment at which the first data block arrives at a medium dependent interface MDI of the sending apparatus, and generating a sending timestamp, where the sending timestamp is used to record a sending moment of the first clock synchronization packet; generating a second clock synchronization packet carrying the sending timestamp; and sending, by the sending apparatus, the second clock synchronization packet.

A communication system comprises a clock generator configured to generate a plurality of system clock signals used to synchronize components included in each of communication nodes in the communication system based on an external clock signal provided by an external clock source located outside the communication system and a physical layer configured to transmit any one of the generated system clock signals to a small cell communicatively connected to an end communication node of the communication system.

In one embodiment, a method receives a first time from a network device. The first time is derived from a first timing source in a first domain. The method receives a second time in a second domain from a second timing source. A difference time value is calculated between the first time and the second time. The method then sends the difference time value to the network device where the network device uses the difference time value to send a delay value to other computing devices to synchronize timing of the other computing devices in the second domain. The other computing devices are configured to synchronize the respective time using the delay value with mobile network devices to allow timing synchronization between the mobile network devices.

In one embodiment, a system receives a number of times from a number of time sources including sensors and real-time clocks (RTCs), wherein the sensors are in communication with the ADV and the sensors include at least a GPS sensor, and where the RTCs include at least a central processing unit real-time clock (CPU-RTC). The system generating a difference histogram based on a time for each of the time sources for a difference between a time of the GPS sensor and a time for each of the other sensors and RTCs. The system ranks the sensors and RTCs based on the difference histogram. The system selects a time source from one of the sensors or RTCs with a least difference in time with respect to the GPS sensor. The system generates a timestamp based on the selected time source to timestamp sensor data for a sensor unit of the ADV.

A system on a chip (SOC) is configured to support multiple time domains within a time-sensitive networking (TSN) environment. TSN extends Ethernet networks to support a deterministic and high-availability communication on Layer 2 (data link layer of open system interconnect OSI model) for time coordinated capabilities such as industrial automation and control applications. Processors in a system may have an application time domain separate from the communication time domain. In addition, each type time domain may also have multiple potential time masters to drive synchronization for fault tolerance. The SoC supports multiple time domains driven by different time masters and graceful time master switching. Timing masters may be switched at run-time in case of a failure in the system. Software drives the SoC to establish communication paths through a sync router to facilitate communication between time providers and time consumers. Multiple time sources are supported.

A system for a network of one or more off-board subsystems is provided for controlling automobile subsystems such as vehicle lighting. Such a system may be compatible with a universal asynchronous receiver transmitter (UART) interface and it may address timing issues by using a protocol having a synchronization frame (sync frame) such that a clock signal may be recovered from the sync frame sent by an off-board master device 202, such as a microcontroller unit 208, to a satellite/slave 211 device. Such a protocol permits elimination of a crystal clock oscillator and phase-locked loop located at satellite, thereby dispensing with an otherwise significant cost.