In one embodiment, a method receives a first time from a network device. The first time is derived from a first timing source in a first domain. The method receives a second time in a second domain from a second timing source. A difference time value is calculated between the first time and the second time. The method then sends the difference time value to the network device where the network device uses the difference time value to send a delay value to other computing devices to synchronize timing of the other computing devices in the second domain. The other computing devices are configured to synchronize the respective time using the delay value with mobile network devices to allow timing synchronization between the mobile network devices.

A system on a chip (SOC) is configured to support multiple time domains within a time-sensitive networking (TSN) environment. TSN extends Ethernet networks to support a deterministic and high-availability communication on Layer 2 (data link layer of open system interconnect OSI model) for time coordinated capabilities such as industrial automation and control applications. Processors in a system may have an application time domain separate from the communication time domain. In addition, each type time domain may also have multiple potential time masters to drive synchronization for fault tolerance. The SoC supports multiple time domains driven by different time masters and graceful time master switching. Timing masters may be switched at run-time in case of a failure in the system. Software drives the SoC to establish communication paths through a sync router to facilitate communication between time providers and time consumers. Multiple time sources are supported.

A shared bus time interleaves 1 PPS signal and control and coordination information between a primary timing source and line cards that need to be synchronized using the 1 PPS signals. The shared bus utilizes 1 second frames divided into time slots. The 1 PPS signals are interleaved at predetermined locations in the frame so the delays introduced by interleaving the 1 PPS data in time can be precisely removed. While the bus is not being used for 1 PPS signals, the bus is available to send control and coordination information between the line cards and the primary timing source, avoiding the use of another system and increasing utilization of an available communication path.

A method (10) of encapsulating digital communications signals for transmission on a communications link, comprising steps: a. receiving a first signal of a first signal type and comprising a first clock signal and receiving a second signal of a second signal type, different to the first, and comprising a second clock signal different to the first clock signal, each clock signal having a respective clock value and accuracy (12); b. obtaining the first clock signal (14); c. obtaining a difference between at least one of the clock values of the clock signals and the accuracies of the clock signals (16) and buffering the second signal for a time at least long enough to compensate for the difference (18); and d. assembling the first signal and the buffered second signal into a frame comprising an overhead and a payload comprising a first portion and a second portion, mapping the first signal into the first portion and the second signal into the second portion (20), wherein step d. is performed using the first clock signal.

Techniques for generating a fail safe clock signal improves reliability of one or more output clock signals generated based on one or more input clock signals and an internally generated reference clock signal. By continuously monitoring the frequencies of the one or more input clock signals and reducing or eliminating effects of any static frequency offset between multiple input clock signals, the fail safe clock generator can detect very small relative frequency changes between the inputs or within a particular input. By comparing the input clock frequencies against a reference clock signal frequency over time of a clock signal generated by an internal oscillator, the fail safe clock generator may further detect which one of multiple input clocks has frequency deviation. The fail safe clock generator uses an internal oscillator generating a reference clock signal having a short-term stable frequency.

A device and a method for supporting clock transfer of multiple clock domains, where the device includes N phase frequency detectors, N filters, N clock reconstructors, and N clock domain interfaces, where N is an integer greater than or equal to two, the N clock domain interfaces are in a one-to-one correspondence with the N phase frequency detectors, the N filters, and the N clock reconstructors, the N phase frequency detectors are respectively connected to N clock sources, and at least two clock sources of the N clock sources are different. The foregoing device flexibly adapt to multiple different clock domains, implement that a single device simultaneously supports clock transfer of multiple clock domains, and flexibly satisfy user demands without adding or replacing devices.

The present disclosure provides a network switch device and a method of operating the same. The network switch device includes a first port, a second port and a processing device. The first port receives a first clock signal, wherein the first port has a first interface including a first interface number. The second port receives a second clock signal, wherein the second port has a second interface including a second interface number, wherein the first clock signal and the second clock signal have the same quality level. The processing device selects a reference clock signal for synchronization from the first clock signal and the second clock signal based on the first interface number and the second interface number.

A system may include a plurality of devices coupled to one another via a shared digital wired communication link, the plurality of devices comprising a first device configured to periodically transmit a synchronization packet onto the shared digital wired communication link to synchronize other of the plurality of devices to a reference clock of the first device, a second device configured to receive the synchronization packet and transmit one or more first data packets onto the shared digital wired communication link in response to the synchronization packet, and a third device configured to receive the synchronization packet and transmit one or more second data packets onto the shared digital wired communication link in response to the synchronization packet and the one or more second data packets.

A method is disclosed for use by a network element comprising a plurality of ports for communicating a common clock signal with one or more neighboring network elements. The method comprises, for at least one port of the plurality of ports, determining, while the port is in a predefined listening mode, whether the port is connected with a neighboring network element; and calculating, when the port is connected, a respective clock phase delay value between the network element and the neighboring network element. The method further comprises, based on a role assigned to the network element from a plurality of predefined roles, assigning a clock signal synchronization role to the port. The network element is configured to communicate the common clock signal using the clock phase delay value and using the clock signal synchronization role.

A device and a method for supporting clock transfer of multiple clock domains, where the device includes N phase frequency detectors, N filters, N clock reconstructors, and N clock domain interfaces, where N is an integer greater than or equal to two, the N clock domain interfaces are in a one-to-one correspondence with the N phase frequency detectors, the N filters, and the N clock reconstructors, the N phase frequency detectors are respectively connected to N clock sources, and at least two clock sources of the N clock sources are different. The foregoing device flexibly adapt to multiple different clock domains, implement that a single device simultaneously supports clock transfer of multiple clock domains, and flexibly satisfy user demands without adding or replacing devices.