A physical layer circuit of a receiver, a clock recovery circuit and a calibration method of frequency offset are provided. The physical layer circuit includes an equalizer and a clock recovery circuit. The equalizer generates an equalized sampling signal corresponding to a sampling clock signal. The clock recovery circuit includes a phase detector, a loop filter, a free wheel circuit, an output circuit and a controller. The phase detector calculates phase differences according to the equalized sampling signal. The loop filter generates loop pulses according to the phase differences. The free wheel circuit generates free wheel pulses. The output circuit receives the loop pulses and the free wheel pulses and generates corresponding phase-shifting pulses for adjusting the sampling clock signal. The controller calculates an accumulative correction offset according to the phase-shifting pulses, and the free wheel circuit periodically generates the free wheel pulses accordingly.

A physical layer circuit of a receiver, a clock recovery circuit and a calibration method of frequency offset are provided. The physical layer circuit includes an equalizer and a clock recovery circuit. The equalizer generates an equalized sampling signal corresponding to a sampling clock signal. The clock recovery circuit includes a phase detector, a loop filter, a free wheel circuit, an output circuit and a controller. The phase detector calculates phase differences according to the equalized sampling signal. The loop filter generates loop pulses according to the phase differences. The free wheel circuit generates free wheel pulses. The output circuit receives the loop pulses and the free wheel pulses and generates corresponding phase-shifting pulses for adjusting the sampling clock signal. The controller calculates an accumulative correction offset according to the phase-shifting pulses, and the free wheel circuit periodically generates the free wheel pulses accordingly.

A sensor synchronization system for an autonomous vehicle is described. Upon initializing a master clock on a master processing node for a sensor apparatus of the autonomous vehicle, the system determines whether an external timing signal is available. If the signal is available, the system synchronizes the master clock with the external timing signal. Based on a clock cycle of the master clock, the system propagates timestamp messages to the sensors of the sensor apparatus, receives sensor data, and formats the sensor data based on the timestamp messages.

A device and a method for supporting clock transfer of multiple clock domains, where the device includes N phase frequency detectors, N filters, N clock reconstructors, and N clock domain interfaces, where N is an integer greater than or equal to two, the N clock domain interfaces are in a one-to-one correspondence with the N phase frequency detectors, the N filters, and the N clock reconstructors, the N phase frequency detectors are respectively connected to N clock sources, and at least two clock sources of the N clock sources are different. The foregoing device flexibly adapt to multiple different clock domains, implement that a single device simultaneously supports clock transfer of multiple clock domains, and flexibly satisfy user demands without adding or replacing devices.

Provided are systems and methods for implementing a reliable precision time architecture in a network device. In various implementations, a first port of the network device can be configured to synchronize to a first network time from the network. A second port can be configure to receive the first network time from the first port, and further provide the first network time to the network. A third port of the network device can further be configured to synchronize to a second network time from the network. A fourth port can be configured to receive the second network time from the third port, and provide the second network time to the network. The network device can further be configured to use the first network time as a current time.

Provided are systems and methods for a reliable precision time architecture in a network. In various implementations, the network can be configured with a first time synchronization tree, the first time synchronization tree providing a first network time to network devices in the network. Each network device can further synchronize to the first network time. The network can further be configured with a second time synchronization tree. The second time synchronization tree can provide a second network time to the network devices on the network. The network devices can also synchronize to the second network time. The network devices can further be configured to use the first network time as a current time.

A Managed Timing Engine (MTE) provides a primary timing output synchronized to a selected input reference from a multiplicity of input references. Additional timing outputs can be generated such that there is a programmable frequency offset (in ppb) between them and the main output. The rate (in Hz) of the outputs can be programmable. The MTE can introduce a programmable delay for periodic phase references.

A method (10) of encapsulating digital communications traffic for transmission on an optical link, the method comprising: a. receiving an input digital communications signal having an input line code (12); b. performing clock and data recovery on the input digital communications signal to obtain input line coded digital communications traffic and a recovered clock signal (14); c. decoding the input digital communications traffic to obtain information bits and non-information bits (16); d. removing the non-information bits (18); e. adding service channel bits for monitoring or maintenance (20); f. assembling the service channel bits and information bits into frames (22); and g. line coding the assembled frames using an output line code to form an encapsulated digital communications signal for transmission on an optical link (24), wherein steps c. to g. are performed using the timing of the recovered clock signal. A communications network receiver configured to implement the method is also provided.

Systems and methods for detecting the failure of a precision time source using an independent time source are disclosed. Additionally, detecting the failure of a GNSS based precision time source based on a calculated location of a GNSS receiver is disclosed. Moreover, the system may be further configured to distribute a time derived from the precision time source as a precision time reference to time dependent devices. In the event of a failure of the precision time source, the system may be configured to distribute a time derived from a second precision time source as the precision time signal during a holdover period.

Various embodiments relate to a network node and method thereof including a high stability oscillator and a holdover phase-locked loop (PLL) wherein the holdover PLL is configured to perform a holdover function by receiving a system clock signal, disciplining the high stability oscillator using the system clock signal to generate a local reference signal, and providing the local reference signal as the system clock signal when the system clock signal becomes unavailable.