A method and structure for equalization in coherent optical receivers. Block-based LMS (BLMS) algorithm is one of the many efficient adaptive equalization algorithms used to (i) increase convergence speed and (ii) reduce implementation complexity. Since the computation of the equalizer output and the gradient of the error are obtained using a linear convolution, BLMS can be efficiently implemented in the frequency domain with the constrained frequency-domain BLMS (FBLMS) adaptive algorithm. The present invention introduces a novel reduced complexity constrained FBLMS algorithm. This new approach replaces the two discrete Fourier transform (DFT) stages required to evaluate the DFT of the gradient error, by a simple frequency domain filtering. Implementation complexity can be drastically reduced in comparison to the standard constrained FBLMS. Furthermore, the new approach achieves better performance than that obtained with the unconstrained FBLMS in ultra-high speed coherent optical receivers.

Methods, systems and devices for lattice reduction in decision feedback equalizers for orthogonal time frequency space (OTFS) modulation are described. An exemplary wireless communication method, implementable by a wireless communication receiver apparatus, includes receiving a signal comprising information bits modulated using OTFS modulation scheme. Each delay-Doppler bin in the signal is modulated using a quadrature amplitude modulation (QAM) mapping. The method also includes estimating the information bits based on an inverse of a single error covariance matrix of the signal, with the single error covariance matrix being representative of an estimation error for all delay-Doppler bins in the signal.

According to one embodiment, a communication device includes a control circuit. The control circuit determines an output waveform of the data to be received from an external device. The control circuit stores information relating to the output waveform into a nonvolatile memory in response to determining of the output waveform of the data from among N (N is a natural number of three or more) types of output waveforms. The control circuit determines an output waveform of the data from among M or less types of output waveforms in the N types of output waveforms (M<N) (M is a natural number of N−2 or more) based on the information stored in the nonvolatile memory, when the information is stored in the nonvolatile memory.

A high bandwidth continuous time linear equalization (HBCTLE) circuit is disclosed. The HBCTLE circuit includes a continuous time linear equalization (CTLE) circuit and a gain circuit coupled with an output of the CTLE circuit. A feedback circuit is coupled between the output of the CTLE circuit and an output of the gain circuit.

A calibration method of an equalizer circuit for a memory storage device is disclosed. The calibration method includes: receiving a first signal; adjusting, by the equalizer circuit, the first signal according to a control parameter to output a second signal; generating a first sampling signal according to a first reference signal and the second signal, wherein the first sampling signal reflects data transmitted by the first signal; and generating a second sampling signal according to a second reference signal and the second signal and adjusting the control parameter according to the second sampling signal to calibrate the equalizer circuit, wherein a voltage value of the first reference signal is different from a voltage value of the second reference signal.

A fixed wireless access radio is disclosed that is compact, light and low power for street level mounting, operates at 100 Mb/s or higher at ranges of 300 m or longer in obstructed LOS conditions with low latencies of 5 ms or less, can support PTP and PMP topologies, uses radio spectrum resources efficiently and does not require precise physical antenna alignment.

A high-speed signaling system with adaptive transmit pre-emphasis. A transmit circuit has a plurality of output drivers to output a first signal onto a signal path. A receive circuit is coupled to receive the first signal via the signal path and configured to generate an indication of whether the first signal exceeds a threshold level. A first threshold control circuit is coupled to receive the indication from the receive circuit and configured to adjust the threshold level according to whether the first signal exceeds the threshold level. A drive strength control circuit is coupled to receive the indication from the receive circuit and configured to adjust a drive strength of at least one output driver of the plurality of output drivers according to whether the first signal exceeds the threshold level.

A logging tool is positioned downhole in a wellbore, where the logging tool communicates with a computer on the Earth's surface over an analog signal path. Tool data is received from a sensor associated with the logging tool and encoded into a symbol signal. The symbol signal is transmitted to a receiver system via the analog signal path. The receiver system has one or more filters to filter the symbol signal. The one or more filters includes an equalizer filter indicative of an analog signal path response of the analog signal path. The filtered symbol signal is decoded into second tool data. The second tool data is encoded into second symbols and based on the second symbols, an updated analog signal path response of the analog signal path is generated to update the equalizer filter.

An integrated circuit may include a receiver configured to receive a first data signal based on an m.sup.th (where m is an integer of 1 or more) transmitter preset setting among a plurality of transmitter preset settings through an external link, and equalize and sample the first data signal; a receiver setting table including a plurality of combinations including values of a plurality of parameters related to the receiver; and a receiver control circuit configured to sequentially select the plurality of combinations with reference to the receiver setting table and set the plurality of parameters with the selected combinations.

A method and structure for a coherent optical receiver device. Timing recovery (TR) is implemented after channel dispersion (i.e., chromatic dispersion (CD) and polarization mode dispersion (PMD)) compensation blocks. This architecture provides both improves performance and reduces power consumption of the device. Also, a TR loop is provided, enabling computing, by an error evaluation module, a first sampling phase error (SPE) and computing, by a timing phase information (TPI) module coupled to the error evaluation module, a second SPE from a plurality of CD equalizer taps PMD equalizer taps. The first and second SPE are combined into a total phase error (TPE) in a combining module, and the resulting TPE is filtered by a timing recovery (TR) filter coupled to an interpolated timing recovery (ITR) module and the combining module. The ITR module then synchronizes an input signal of the coherent optical receiver according to the TPE.