Methods, apparatus, and systems for calibration and correction of data communications over a multi-wire, multi-phase interface are disclosed. In particular, calibration is provided for data communication devices coupled to a 3-line interface. The calibration includes generating and transmitting a calibration pattern on the 3-line interface, where the generation of the pattern includes toggling two of three interface lines from one voltage level to another voltage level over a predetermined time interval. Furthermore, the generation of the pattern includes maintaining a remaining third interface line at a common mode voltage level over the predetermined time interval, wherein only a single transition occurs for the predetermined time interval. Calibration data may then be derived in a receiver device using the transmitted calibration pattern.

Apparatuses and methods for multi-level communication architectures are disclosed herein. An example apparatus may include a driver circuit configured to convert a plurality of bitstreams into a plurality of multilevel signals. A count of the plurality of bitstreams is greater than count of the plurality of multilevel signals. The driver circuit further configured to drive the plurality of multilevel signals onto a plurality of signal lines using individual drivers. A driver of the individual drivers is configured to drive more than two voltages.

Data communication apparatus and methods for a multi-wire interface are disclosed. A half rate clock and data recovery (CDR) circuit derives a clock signal including pulses corresponding to symbols transmitted on a 3-wire interface, where the symbols are transmitted at a particular frequency with each of the symbols occurring over a unit interval (UI) time period. The first clock signal is input to a flip-flop logic included in a delay loop, and serves to trigger the first flip-flop logic. A second clock signal is generated using a programmable generator in the delay loop and has a frequency of a half UI and is fed back to a data input of the flip-flop. The output of the flip-flop is used as a recovered clock signal for the CDR at a half rate frequency. This design provides ease of timing control, a delay line without extra nonlinear-effects, and less hardware overhead.

The present invention describes a method and system for simultaneous transmission of data to coherent and non-coherent receivers. The method at the transmitter includes retrieving a base ternary sequence having a pre-defined length, obtaining one or more ternary sequences corresponding to data to be transmitted and transmitting the obtained one or more ternary sequences by the transmitter. The method steps at the receiver includes receiving one or more ternary sequences corresponding to the data transmitted, demodulating each of the received ternary sequences by correlating with all cyclic shifts of the base ternary sequence by the receiver if the receiver is a coherent receiver, demodulating each of the received ternary sequences by correlating with all cyclic shifts of the absolute of the base ternary sequence by the receiver if the receiver is a non-coherent receiver and detecting the transmitted data based on the cyclic shifts corresponding to maximum correlation values.

A transmission device according to the disclosure includes a power supply section, a first transmitter, and a controller. The power supply section includes a voltage generator that generates a power supply voltage, and a load section configured to be able to change a load current at the voltage generator. The first transmitter has a first operation mode and a second operation mode, and transmits a first signal on the basis of the power supply voltage. The controller controls an operation of the load section when an operation mode of the first transmitter transitions between the first operation mode and the second operation mode.

The present invention describes a method and system for simultaneous transmission of data to coherent and non-coherent receivers. The method at the transmitter includes retrieving a base ternary sequence having a pre-defined length, obtaining one or more ternary sequences corresponding to data to be transmitted and transmitting the obtained one or more ternary sequences by the transmitter. The method steps at the receiver includes receiving one or more ternary sequences corresponding to the data transmitted, demodulating each of the received ternary sequences by correlating with all cyclic shifts of the base ternary sequence by the receiver if the receiver is a coherent receiver, demodulating each of the received ternary sequences by correlating with all cyclic shifts of the absolute of the base ternary sequence by the receiver if the receiver is a non-coherent receiver and detecting the transmitted data based on the cyclic shifts corresponding to maximum correlation values.

A method and interface circuit for testing an electronic device with a single logic pin is disclosed. The comprises forming a data stream having three level bands; inputting the data stream through a single logic pin; and decoding the data stream to identify a scan_in signal, a scan_shift_enable signal and a scan_out signal and returning contemporaneously a scan_out signal as an output through the same logic pin. The interface circuit includes a decoder connected to the single logic pin.

A transmission device according to the disclosure includes: a controller that selects one of a plurality of operation modes; and a first transmitter that includes a first capacitance setting section that sets a load capacitance in accordance with an operation mode selected by the controller, and is configured to be able to output, to a first output terminal, a first signal having a signal format according to the selected operation mode, among a plurality of signal formats.

Described are apparatuses and methods for reducing channel physical layer (C-PHY) switching jitter. An apparatus may include a pattern dependent delay circuit to detect a switching pattern of at least three data signals on respective wires and adaptively change delays of the at least three data signals based on the switching pattern. The apparatus may further include a transmitter, coupled to the pattern dependent delay circuit, to transmit the at least three data signals.

A data transmission and reception system may include: a data transmission apparatus configured to generate N Tx signals having discrete levels using N binary data, and output the N Tx signals to N single-ended signal lines, respectively, where N is a natural number equal to or larger than 2; and a data reception apparatus configured to receive the N Tx signals transmitted in parallel through the single-ended signal lines, and restore the N binary data by comparing the received N Tx signals to each other.