A perovskite material that has a perovskite crystal lattice having a formula of C.sub.xM.sub.yX.sub.z, and alkyl polyammonium cations disposed within or at a surface of the perovskite crystal lattice; wherein x, y, and z, are real numbers; C comprises one or more cations selected from the group consisting of Group 1 metals, Group 2 metals, ammonium, formamidinium, guanidinium, and ethene tetramine; M comprises one or more metals each selected from the group consisting of Be, Mg, Ca, Sr, Ba, Fe, Cd, Co, Ni, Cu, Ag, Au, Hg, Sn, Ge, Ga, Pb, In, Tl, Sb, Bi, Ti, Zn, Cd, Hg, and Zr, and combinations thereof; and X comprises one or more anions each selected from the group consisting of halides, pseudohalides, chalcogenides, and combinations thereof.

A charge trapping non-volatile organic memory device according to the present invention has a structure in which an organic matter-based blocking layer, a trapping layer, and a tunneling layer are sequentially positioned between a gate and an organic semiconductor layer positioned on an insulating substrate, the trapping layer including a metal oxide and a polymer, and has an organic-inorganic composite film in which the metal oxide is dispersed in a polymer matrix in units of atoms.

A semiconductor device can be prepared using a precursor dielectric composition that comprises: (1) a photochemically or thermally crosslinked product of a photocurable or thermally curable thiosulfate-containing polymer that has a T.sub.g of at least 50 C. and that comprises: an organic polymer backbone comprising (a) recurring units comprising pendant thiosulfate groups; and further comprises charge balancing cations, and (2) optionally, an electron-accepting photo sensitizer component. The electronic device can be prepared by independently applying the precursor dielectric composition and an organic semiconductor composition to a substrate to form an applied precursor dielectric composition and an applied organic semiconductor composition, respectively, and subjecting the applied precursor dielectric composition to curing conditions to form a gate dielectric layer that is in physical contact with the applied organic semiconductor composition.

A field effect transistor includes a carbon nanotube layer formed adjacent to a gate structure. Two intermetallic contacts are formed on the carbon nanotube layer. The two intermetallic contacts include an oxidation resistant compound having a work function below about 4.4 electron-volts.

An insulating ink includes a nanoparticle bonded with a substituent having a polymerizable functional group, at least one of an organosilane compound and polyorganosiloxane, and a solvent.

A display apparatus includes a plurality of pixels each including a substrate on which are disposed: an interlayer insulating layer; a driving thin film transistor in which a driving semiconductor layer and a driving gate electrode are each disposed between the substrate and the first interlayer insulating layer; a first capacitor in which a first electrode, a first dielectric pattern and a second electrode are sequentially stacked, the first electrode being connected to the driving gate electrode; and a plurality of contact plugs extended through a thickness of the interlayer insulating layer, with which the driving thin film transistor and the first capacitor are respectively connected to electrodes outside thereof. Lateral surfaces of the first dielectric pattern are covered by the interlayer insulating layer, and the first dielectric pattern within the first capacitor is disposed spaced apart from each of the contact plugs.

A display apparatus includes a plurality of pixels each including a substrate on which are disposed: an interlayer insulating layer; a driving thin film transistor in which a driving semiconductor layer and a driving gate electrode are each disposed between the substrate and the first interlayer insulating layer; a first capacitor in which a first electrode, a first dielectric pattern and a second electrode are sequentially stacked, the first electrode being connected to the driving gate electrode; and a plurality of contact plugs extended through a thickness of the interlayer insulating layer, with which the driving thin film transistor and the first capacitor are respectively connected to electrodes outside thereof. Lateral surfaces of the first dielectric pattern are covered by the interlayer insulating layer, and the first dielectric pattern within the first capacitor is disposed spaced apart from each of the contact plugs.

Printable and stretchable thin-film devices and fabrication techniques are provided for forming fully-printed, intrinsically stretchable thin-film transistors and integrated logic circuits using stretchable elastomer substrates such as polydimethylsiloxane (PDMS), semiconducting carbon nanotube network as channel, unsorted carbon nanotube network as source/drain/gate electrodes, and BaTiO.sub.3/PDMS composite as gate dielectric. Printable stretchable dielectric layer ink may be formed by mixing barium titanate nanoparticle (BaTiO.sub.3) with PDMS using 4-methyl-2-pentanone as solvent.

An organic CMOS circuit including a substrate having an N-type organic transistor and a P-type organic transistor formed thereon, the transistors respectively including a layer of N-type semiconductor material and a layer of P-type semiconductor material. A surface of each of the semiconductor material layers, opposite to the substrate, is covered with an anti-ultraviolet layer made of electrically-insulating material absorbing and/or reflecting ultra-violet rays.

The present invention relates to vessels comprising a formulation including at least one organic semiconductor, wherein the formulation is in contact with at least one absorption material. The invention further describes a process for producing the vessel and for the use thereof.