A substrate processing apparatus includes: a first holding part configured to hold a substrate; a second holding part configured to hold the substrate; a sliding member configured to rotate about a vertical axis so that the sliding member slides on a back surface of the substrate; a revolution mechanism configured to revolve the sliding member under rotation about a vertical revolution axis; and a relative movement mechanism configured to horizontally move a relative position between the substrate and a revolution trajectory of the sliding member so that when the substrate is held by the first holding part, the sliding member slides on a central portion of the back surface of the substrate, and when the substrate is held by the second holding part, the sliding member slides on the peripheral portion of the back surface of the substrate under rotation.

Some embodiments relate to a method. In this method, a semiconductor wafer having a frontside and a backside is received. A frontside structure is formed on the frontside of the semiconductor wafer. The frontside structure exerts a first wafer-bowing stress that bows the semiconductor wafer by a first bow amount. A characteristic is determined for one or more stress-inducing films to be formed based on the first bow amount. The one or more stress-inducing films are formed with the determined characteristic on the backside of the semiconductor wafer and/or on the frontside of the semiconductor wafer to reduce the first bow amount in the semiconductor wafer.

A method of fabricating a semiconductor device includes forming a first semiconductor region at a front surface of a substrate, the first semiconductor region including an active element that regulates current flowing in a thickness direction of the substrate; grinding a rear surface of the substrate; after the grinding, performing a first etching that etches the rear surface of the substrate with a chemical solution including phosphorus; after the first etching, performing a second etching that etches the rear surface with an etching method with a lower etching rate than the first etching; and after the second etching, forming a second semiconductor region through which the current is to flow, by implanting impurities from the rear surface of the substrate.

A processing chamber system includes a substrate mounting module configured to secure a substrate within a first processing chamber. The system also includes a first deposition module configured to apply a light-sensitive film to a front side surface of the substrate, and a second deposition module configured to apply a film layer to a backside surface of the substrate. The front side surface is opposite to the backside surface of the substrate. A substrate has a bare backside surface with a first coefficient of friction. A film layer is formed onto the backside surface of the substrate. The film layer formed on the backside surface of the substrate has a second coefficient of friction. The second coefficient of friction is lower than the first coefficient of friction.

A semiconductor wafer has a base material with a first thickness and first and second surfaces. A wafer scribe mark is disposed on the first surface of the base material. A portion of an interior region of the second surface of the base material is removed to a second thickness less than the first thickness, while leaving an edge support ring of the base material of the first thickness and an asymmetric width around the semiconductor wafer. The second thickness of the base material is less than 75 micrometers. The wafer scribe mark is disposed within the edge support ring. The removed portion of the interior region of the second surface of the base material is vertically offset from the wafer scribe mark. A width of the edge support ring is wider to encompass the wafer scribe mark and narrower elsewhere around the semiconductor wafer.

Embodiments of semiconductor structures for wafer flatness control and methods for using and forming the same are disclosed. In an example, a model indicative of a flatness difference of a wafer between a first direction and a second direction is obtained. The flatness difference is associated with one of a plurality of fabrication stages of a plurality of semiconductor devices on a front side of the wafer. A compensation pattern is determined for reducing the flatness difference based on the model. At the one of the plurality of the fabrication stages, a compensation structure is formed on a backside opposite to the front side of the wafer based on the compensation pattern to reduce the flatness difference.

A method of manufacturing a semiconductor device that includes a semiconductor element. The method includes the steps of providing a semiconductor substrate of a first conductivity type, forming an element structure of the semiconductor element, at a first main surface of the semiconductor substrate, forming a first protective film at a second main surface of the semiconductor substrate, implanting ions in the semiconductor substrate from the second main surface having the first protective film formed thereon, and removing the first protective film.

Semiconductor substrate thinning systems and methods. Implementations of a method of thinning a semiconductor substrate may include: providing a semiconductor substrate having a first surface and a second surface opposing the first surface and inducing damage into a portion of the semiconductor substrate adjacent to the second surface forming a damage layer. The method may also include backgrinding the second surface of the semiconductor substrate.

Methods and designs are provided for a vertical power semiconductor switch having an IGBT-with-built-in-diode bottom-side structure combined with a SJMOS topside structure in such a way as to provide fast switching with low switching losses (MOSFET), low on-resistance at low currents (SJMOS), low on-resistance at high currents (IGBT), and high current-density capability (IGBT).

A semiconductor wafer has a base material with a first thickness and first and second surfaces. A wafer scribe mark is disposed on the first surface of the base material. A portion of an interior region of the second surface of the base material is removed to a second thickness less than the first thickness, while leaving an edge support ring of the base material of the first thickness and an asymmetric width around the semiconductor wafer. The second thickness of the base material is less than 75 micrometers. The wafer scribe mark is disposed within the edge support ring. The removed portion of the interior region of the second surface of the base material is vertically offset from the wafer scribe mark. A width of the edge support ring is wider to encompass the wafer scribe mark and narrower elsewhere around the semiconductor wafer.