Semiconductor device fabrication method and semiconductor device

Abstract

A method of fabricating a semiconductor device includes forming a first semiconductor region at a front surface of a substrate, the first semiconductor region including an active element that regulates current flowing in a thickness direction of the substrate; grinding a rear surface of the substrate; after the grinding, performing a first etching that etches the rear surface of the substrate with a chemical solution including phosphorus; after the first etching, performing a second etching that etches the rear surface with an etching method with a lower etching rate than the first etching; and after the second etching, forming a second semiconductor region through which the current is to flow, by implanting impurities from the rear surface of the substrate.

Claims

1. A method of fabricating a semiconductor device in which current flows in a thickness direction of a substrate, the method comprising: forming an active element on a front surface of the substrate; forming a damaged layer on a rear surface of the substrate; etching the rear surface of the substrate self-consistently by a chemical solution to remove the damaged layer; removing impurities adhered to the substrate in association with the removing of the damaged layer; forming a buffer layer by implanting ions from the rear surface of the substrate; and implanting p-type impurities from the rear surface of the substrate to form a semiconductor region, wherein a density per unit volume of the p-type impurities in the semiconductor region is at most of a density of impurities in the buffer layer.

2. The method according to claim 1, wherein the active element regulates current flowing in the thickness direction of the substrate.

3. The method according to claim 1, wherein the damaged layer is introduced by mechanical grinding.

4. The method according to claim 1, wherein the etching of the rear surface makes irregularities caused by the forming of the damaged layer into a smooth mirror finish.

5. The method according to claim 1, wherein the removing of the impurities comprises washing the substrate with hydrofluoric acid.

6. The method according to claim 1, wherein the etching of the rear surface includes removing the damaged layer by a wet etching solution, and wherein the removing of the impurities includes removing impurities contained in the wet etching solution.

7. The method according to claim 1, wherein the etching of the rear surface of the substrate comprises wet etching using a mixed chemical solution containing phosphoric acid (H.sub.3PO.sub.4).

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) Exemplary embodiments of the present invention will be described in detail based on the following figures, wherein:

(2) FIG. 1 is a graph showing an example of a relationship between a V.sub.ce(sat)E.sub.off characteristic of an IGBT and collector density;

(3) FIG. 2 is a graph showing an example of densities of phosphorus after rear surface wet etching;

(4) FIG. 3 is a vertical sectional diagram showing an example of a semiconductor device in accordance with an exemplary embodiment;

(5) FIG. 4 is a flowchart for describing an example of steps in the fabrication of a semiconductor device in accordance with the exemplary embodiment;

(6) FIG. 5A, FIG. 5B, FIG. 5C and FIG. 5D are vertical sectional diagrams supporting the description of the example of steps in the fabrication of the semiconductor device in accordance with the exemplary embodiment;

(7) FIG. 6 is a graph showing densities of phosphorus in a semiconductor device according to an Example 1; and

(8) FIG. 7 is a graph showing densities of impurities in a semiconductor device according to an Example 2.

DETAILED DESCRIPTION

(9) FIG. 3 illustrates a vertical sectional diagram of a semiconductor device 10 in accordance with an exemplary embodiment. The semiconductor device 10 is an IGBT with a trench gate architecture, which serves as an example of a semiconductor device. The semiconductor device 10 is provided with an active region (an insulated gate structure) that regulates current flowing in the thickness direction of a substrate, including a trench gate 24, a gate oxide film 22, an N-type emitter layer 18, a P-type channel layer 20, an interlayer film 16, a front surface metal electrode 12 and a protective film 13. Below the active region, an N-type substrate 26, a buffer layer (field stop (FS) layer) 28, a P-type collector layer 30 and a rear surface metal electrode 32 are provided. As an example, a silicon substrate is used as the N-type substrate 26.

(10) In the semiconductor device 10, when a voltage is applied to the trench gate 24, electrons from the N-type emitter layer 18 are injected through the P-type channel layer 20 into the N-type substrate 26 (which functions as a drift layer), and holes from the P-type collector layer 30 are injected into the N-type substrate 26. As a result, a conductivity modulation effect occurs in the N-type substrate 26, the resistance is greatly reduced, and large currents may flow. At this time, the buffer layer 28 functions to stop a depletion layer from widening in the N-type substrate 26.

(11) An object with the semiconductor device 10 according to the present exemplary embodiment is to assuredly achieve the removal of undesired impurities, which are not shown in the drawings, that adhere to the N-type substrate 26 in association with etching of the N-type substrate 26, and to enable precise design of a density profile of impurities in the P-type collector layer 30.

(12) Herebelow, a fabrication method of the semiconductor device in accordance with the present exemplary embodiment is described using FIG. 4 and FIG. 5A to FIG. 5D.

(13) First, in step 400 of FIG. 4, the above-described active region is formed at the front surface of the silicon substrate.

(14) Next, in step 402, mechanical grinding is applied to the rear surface of the silicon substrate. This grinding may be carried out using, for example, an infeed grinder.

(15) Then, in step 404, after the grinding, wet etching is applied to the rear surface of the silicon substrate. Here, an etching chemical solution that is employed may be, for example, a mixed chemical solution including hydrofluoric acid, nitric acid and sulfuric acid. The functions of the acids in this mixed chemical solution are as described above.

(16) Then, in step 406, the rear surface of the silicon substrate that has been subjected to the wet etching is washed with hydrofluoric acid.

(17) In step 408, SC-1 washing is applied to the rear surface of the silicon substrate. A cross-section of the substrate at this time is shown in FIG. 5A.

(18) The term SC-1 washing used herein is intended to include washing with washing solutions containing aqueous ammonia and aqueous hydrogen peroxide, by a washing method in which a surface of a silicon substrate is first oxidized by aqueous hydrogen peroxide, after which the silicon oxide is etched with the alkaline ammonia, and various particles adhering to the silicon oxide are removed by lift-off.

(19) The washing with hydrofluoric acid in step 406 and the SC-1 washing in step 408 are steps that remove phosphorus contamination associated with the wet etching. The washing with hydrofluoric acid and SC-1 washing are both light etching, in which the etching rate is restricted. Thus, the flatness of the rear surface of the silicon substrate provided by the wet etching of step 404 is maintained even while phosphorus adhering to the rear surface of the silicon substrate is removed.

(20) It should be noted that an effect can be obtained even with only one or other of the washing with hydrofluoric acid and the SC-1 washing. Thus, performing both is not necessarily required; just one may be performed, depending on the density of residual phosphorus that can be tolerated. Moreover, the washing with hydrofluoric acid and the SC-1 washing do not necessarily need to be carried out in this order. The washing with hydrofluoric acid may be carried out after the SC-1 washing.

(21) Then, in step 410, after the SC-1 washing, phosphorus ions (31P.sup.+) are implanted into the rear surface of the silicon substrate with an acceleration energy of several hundred keV to form the buffer layer (field stop layer) 28 (FIG. 5B). The buffer layer 28 is formed so as to have a peak of phosphorus density in the N-type substrate 26, that is, in general terms, so as to have a peak in the vicinity of the n.sup.+ label in FIG. 5B.

(22) In step 412, boron ions (11B.sup.+) are implanted into the rear surface of the silicon substrate with an acceleration energy of several tens of keV to form the P-type collector layer 30 (FIG. 5C).

(23) In step 414, laser annealing is applied to the boron in order to activate the boron implanted in step 412.

(24) In step 416, the rear surface metal electrode 32 is formed at the rear surface of the silicon substrate. Thus, the semiconductor device (IGBT) 10 according to the present exemplary embodiment is completed (FIG. 5D).

(25) Thereafter, dicing and the like is performed and chips with appropriate numbers of the semiconductor device 10 are separated out.

Example 1

(26) Four specimens were prepared using silicon substrates, laser annealing was performed, and phosphorus densities were evaluated by SIMS analysis. The thickness after rear surface grinding of the silicon substrates used for the evaluations was approximately 100 m.

(27) Specimen 1: After rear surface grinding, conventional wet etching was performed on the silicon substrate (i.e., step 404 of the fabrication steps in FIG. 4 was carried out). The silicon etching chemical solution was a mixed chemical solution of 10% hydrofluoric acid, 30% nitric acid, 20% sulfuric acid, 20% phosphoric acid and 20% water (proportions by volume), and the etching rate was approximately 20 m/minute. The etching duration was 1 minute, grinding the silicon substrate to approximately 80 m. After the wet etching, a duration of washing with purified water was about 60 seconds.

(28) Specimen 2: After the conventional wet etching described above, the silicon substrate was rinse-washed with purified water for 120 seconds (i.e., the purified water rinse-washing was applied for twice the conventional duration).

(29) Specimen 3: After the conventional wet etching described above, the silicon substrate was washed with hydrofluoric acid (0.3%). The etching rate of this oxide layer etching with hydrofluoric acid was approximately 0.002 m/minute, and the etching duration was 1 minute.

(30) Specimen 4: After the conventional wet etching described above, washing with hydrofluoric acid (0.3%) and SC-1 washing were applied to the silicon substrate. The mixing ratio of the chemical solution of the SC-1 washing was 1 part ammonia (NH.sub.4OH) to 1 part aqueous hydrogen peroxide (H.sub.2O.sub.2) to 10 parts water (H.sub.2O) (proportions by volume). The rate of etching of the silicon was approximately 0.5 nm/minute and the etching duration was 1 minute. The etching rate and etching duration of the oxide layer etching with hydrofluoric acid (0.3%) were the same as for specimen 3.

(31) The results of SIMS analysis of these four specimens are shown in FIG. 6. FIG. 6 shows phosphorus densities, with (a) corresponding to specimen 1, (b) corresponding to specimen 2, (c) corresponding to specimen 3 and (d) corresponding to specimen 4.

(32) In specimen 1 produced by the conventional wet etching, shown as (a) in FIG. 6, phosphorus is present in densities of the order of 10.sup.17 atoms/cm.sup.3 to a depth of 0.4 m from the etched surface.

(33) In specimen 2, with twice the duration of rinse-washing with purified water after the wet etching, shown as (b) in FIG. 6, it is apparent that the phosphorus density is a little lower than in specimen 1 but there is no great difference. Therefore, it is likely that phosphorus cannot be thoroughly removed just by rinse-washing with purified water.

(34) In specimen 3 for which washing with hydrofluoric acid is added, shown as (c) in FIG. 6, it is apparent that the phosphorus is greatly reduced, with phosphorus densities of the order of 10.sup.15 atoms/cm.sup.3. Thus, an effect of residual phosphorus being removed by hydrofluoric acid is verified. However, complete removal of the phosphorus is not achieved.

(35) In specimen 4 for which both washing with hydrofluoric acid and SC-1 washing are applied, shown as (d) in FIG. 6, the phosphorus density measurements are of the order of 10.sup.14 atoms/cm.sup.3, which is the lower limit of phosphorus detection of the SIMS. Thus, it is seen that phosphorus is substantially completely removed.

(36) From the evaluation results described above, it can be seen that, if washing with hydrofluoric acid and SC-1 washing are carried out after wet etching with a chemical solution containing phosphorus, residual phosphorus can be substantially completely removed. It can also be seen that substantial amounts of the residual phosphorus can be removed if one or other of the washing with hydrofluoric acid and the SC-1 washing is carried out.

Example 2

(37) A sample of a practical IGBT was prepared and impurity densities therein were measured.

(38) Grinding was applied to the rear surface of a silicon substrate at whose front surface an active region for regulating current flowing in the thickness direction of the substrate had been formed, and the processing according to the above-described specimen 4 was carried out; that is, washing with hydrofluoric acid and SC-1 washing were carried out after usual wet etching. Conditions such as the thickness of the silicon substrate, the etching chemical solutions, the etching rates, the etching durations and so forth were the same as for specimen 4.

(39) At the silicon substrate for which the processing according to specimen 4 had been completed, phosphorus ions (31P.sup.+) were implanted into the rear surface with an acceleration energy of 600 keV to form the buffer layer (field stop layer) 28 (step 410 in FIG. 4). The thickness of the buffer layer 28 was approximately 1.5 m.

(40) Then, boron ions (11B.sup.+) were implanted into the rear surface of the silicon substrate with an acceleration energy of 30 keV to form the P-type collector layer 30 (step 412 in FIG. 4). The thickness of the P-type collector layer 30 was approximately 0.2 m.

(41) Thereafter, laser annealing was applied to the implanted boron (step 414 in FIG. 4).

(42) The results of SIMS analysis of the sample obtained in this manner are shown in FIG. 7.

(43) As can be seen in FIG. 7, the phosphorus density of this sample (the graph marked P in FIG. 7) shows a distribution close to a normal distribution with a peak value of approximately 110.sup.17 atoms/cm.sup.3 at a depth of approximately 0.7 m, which is substantially in accordance with targets. Thus, the effect of phosphorus being removed by the washing with hydrofluoric acid and the SC-1 washing is verified. The phosphorus density in the thickness range of the P-type collector layer 30 (approximately 0.4 m) shows values in the vicinity of 110.sup.16 atoms/cm.sup.3 to 210.sup.16 atoms/cm.sup.3. Thus, it can be seen that the phosphorus density values are suppressed to around of the peak value of 110.sup.17 atoms/cm.sup.3 in the buffer layer 28.

(44) According to the results of Example 1, specimen 1, in which only conventional wet etching was carried out and neither washing with hydrofluoric acid nor SC-1 washing was applied, included around 210.sup.17 atoms/cm.sup.3 of phosphorus to a depth of approximately 0.4 m from the wet-etched rear surface. This density corresponds to 40% of a P-type collector impurity density of 510.sup.17 atoms/cm.sup.3, which is the target for next-generation IGBTs. Residues of phosphorus in such large amounts lead to variations in the impurity densities of the P-type collectors of IGBTs, and are a factor in, for example, large variations in the value of E.sub.off.

(45) In the present sample, as illustrated in FIG. 7, the density of boron in the P-type collector layer 30 (the graph marked B in FIG. 7) is around 310.sup.17 atoms/cm.sup.3. Therefore, the density of phosphorus in the P-type collector layer 30 is about 1/10 of the density of the P-type impurity, boron, in the P-type collector. Thus, because there is an order of magnitude of difference, the effect of phosphorus in the P-type collector layer 30 on the P-type impurities (boron) in the P-type collector layer is small, and precise design of impurity densities in the P-type collector layer 30 is possible.

(46) As is made clear in the descriptions above, according to the semiconductor device 10 in accordance with the present exemplary embodiment, a semiconductor device fabrication method may be provided that assuredly removes undesired impurities that adhere to a semiconductor substrate in association with etching of the semiconductor substrate and that enables precise design of an impurity density profile of the semiconductor substrate, and a semiconductor device that is fabricated by this fabrication method may be provided.

(47) Note that, while it is desirable to implement the removal of phosphorus by washing with hydrofluoric acid and SC-1 washing after wet etching of the rear surface of the silicon substrate, the removal of phosphorus may be carried out before laser annealing, and may be carried out at both stages.

(48) In the exemplary embodiment described above, boron is described as an example of a P-type impurity in the P-type collector, but this is not limiting. Other P-type impurities such as gallium (Ga) and the like may be used.