In one embodiment, a semiconductor device includes a stacked film alternately including a plurality of electrode layers and a plurality of insulating layers. The device further includes a first insulator, a charge storage layer, a second insulator and a first semiconductor layer that are disposed in order in the stacked film. The device further includes a plurality of first films disposed between the first insulator and the plurality of insulating layers. Furthermore, at least one of the first films includes a second semiconductor layer.

A substrate processing method includes a step of supplying a dry processing liquid onto the upper surface of the substrate, to thereby form a liquid film of the dry processing liquid on the upper surface of the substrate (Step S14), a step of heating the substrate from the side of a lower surface thereof in a state where the liquid film of the dry processing liquid is formed on the upper surface thereof (Step S15), and a step of drying the substrate (Step S16). The surface tension of the dry processing liquid is lower than that of the rinse liquid. The boiling point of the dry processing liquid is higher than that of the rinse liquid. The heating temperature of the substrate in Step S15 is not lower than the boiling point of the rinse liquid and lower than that of the dry processing liquid.

A semiconductor substrate includes a surface having a groove. The groove includes an inner bottom surface and an inner wall surface. The inner wall surface has a depression. The depression has a depth from a direction along a surface of the inner wall surface to a width direction of the groove. The substrate being exposed to the inner wall surface.

The present invention addresses the problem of providing novel techniques for manufacturing a SiC substrate that enables reduced material loss when a strained layer is removed. The present invention is a method for manufacturing a SiC substrate 30 which includes a strained layer thinning step S1 for thinning a strained layer 12 of a SiC substrate body 10 by moving the strained layer 12 to a surface side. Including such a strained layer thinning step S1 in which the strain layer is moved to (concentrated toward) the surface side makes it possible to reduce material loss L when removing the strained layer 12.

Provided is a manufacturing method of semiconductor apparatus comprising a semiconductor substrate, the method comprising: grinding a first surface of the semiconductor substrate to form an outer peripheral surplus region on an outer periphery of the semiconductor substrate; and spin etching the first surface of the semiconductor substrate by a chemical liquid, and wherein after the grinding, in a region of the semiconductor substrate which is closer to an inner side than the outer peripheral surplus region, a thickness of the semiconductor substrate in an end portion of the region is greater than a thickness of the semiconductor substrate in a center portion of the region.

A semiconductor wafer and method for manufacturing thereof are provided. The semiconductor wafer includes a handling substrate and a silicon layer over the handling substrate and having a {111} facet at an edge of a top surface of the silicon layer. The a defect count on the top surface of the silicon layer is less than about 15 each semiconductor wafer. The method includes the following operations: a semiconductor-on-insulator (SOI) substrate is provided, wherein the SOI substrate has a handling substrate, a silicon layer over the handling substrate, and a silicon germanium layer over the silicon layer; and the silicon germanium layer is etched at a first temperature with hydrochloric acid to expose a first surface of the silicon layer.

Provided is a method for manufacturing a semiconductor silicon wafer capable of inhibiting P-aggregation defects (Si-P defects) and SF in an epitaxial layer. The method includes a step of forming a silicon oxide film with a thickness of at least 300 nm or thicker only on the backside of the silicon wafer substrate by the CVD method at a temperature of 500° C. or lower after the step of forming the silicon oxide film, a step of heat treatment where the substrate is kept in an oxidizing atmosphere at a constant temperature of 1100° C. or higher and 1250° C. or lower for 30 minutes or longer and 120 minutes or shorter after the heat treatment, a step of removing surface oxide film formed on the front surface of the substrate, and a step of depositing a silicon monocrystalline epitaxial layer on the substrate after the step of removing the surface oxide film.

A silicon carbide substrate has a trench extending from a main surface of the silicon carbide substrate into the silicon carbide substrate. The trench has a trench width at a trench bottom. A shielding region is formed in the silicon carbide substrate. The shielding region extends along the trench bottom. In at least one doping plane extending approximately parallel to the trench bottom, a dopant concentration in the shielding region over a lateral first width deviates by not more than 10% from a maximum value of the dopant concentration. The first width is less than the trench width and is at least 30% of the trench width.

The invention relates to a method of processing a semiconductor in the semiconductor wafer is disposed on a susceptor in a coating apparatus and processed, wherein an etching gas is passed through the coating apparatus in an etching step. The invention further relates to a control system for controlling a coating apparatus for processing a semiconductor water, to a plant for processing a semiconductor wafer having a coating apparatus which comprises the control system, and a semiconductor wafer. A first side of the semiconductor wafer which has been subjected to a polishing operation by CMP, or a second side of the semiconductor wafer opposite the first side, is coated with a protective layer before processing.

The present disclosure is directed to etching compositions that are useful for, e.g., selectively removing silicon germanium (SiGe) from a semiconductor substrate as an intermediate step in a multistep semiconductor manufacturing process.