MANUFACTURING METHOD FOR SEMICONDUCTOR SILICON WAFER

Abstract

Provided is a method for manufacturing a semiconductor silicon wafer capable of inhibiting P-aggregation defects (Si-P defects) and SF in an epitaxial layer. The method includes a step of forming a silicon oxide film with a thickness of at least 300 nm or thicker only on the backside of the silicon wafer substrate by the CVD method at a temperature of 500° C. or lower after the step of forming the silicon oxide film, a step of heat treatment where the substrate is kept in an oxidizing atmosphere at a constant temperature of 1100° C. or higher and 1250° C. or lower for 30 minutes or longer and 120 minutes or shorter after the heat treatment, a step of removing surface oxide film formed on the front surface of the substrate, and a step of depositing a silicon monocrystalline epitaxial layer on the substrate after the step of removing the surface oxide film.

Claims

1. A method for manufacturing a semiconductor silicon wafer composed of a silicon wafer substrate and a silicon monocrystalline epitaxial layer thereon, comprising: a step of forming a silicon oxide film with a thickness of at least 300 nm or thicker only on the backside of the silicon wafer substrate by the CVD method at a temperature of 500° C. or lower, the silicon wafer substrate being manufactured from a silicon single crystal ingot grown by the Czochralski method, being doped with phosphorus, having resistivity being adjusted to be 1.05 mΩ.Math.cm or less, a concentration of solid-solution oxygen of 0.9×10.sup.18 atoms/cm.sup.3 or less, and the front surface of which a silicon monocrystalline epitaxial layer is to be formed on; a step of heat treatment, after the step of forming a silicon oxide film, in which the substrate is kept in an oxidizing atmosphere at a constant temperature of 1100° C. or higher and 1250° C. or lower for 30 minutes or longer and 120 minutes or shorter; a step of removal of surface oxide film, after the step of heat treatment, in which a thermal oxide film formed on the front surface of the substrate; and a step of deposition of a silicon monocrystalline epitaxial layer on the substrate, after the step of removing the surface oxide film.

2. The method for manufacturing a semiconductor silicon wafer in claim 1, wherein the substrate manufactured from the silicon single crystal ingot contains Si-P defects that are formed by aggregation of phosphorus during the growth of the silicon single crystal ingot, a maximum side length of the Si-P defects is less than 100 nm, and a concentration of the Si-P defects is less than 1×10.sup.12/cm.sup.3.

3. The method for manufacturing a semiconductor silicon wafer in claim 1, wherein, in the substrate after the heat treatment in an oxidizing atmosphere, a concentration of phosphorus (P) in a region from the surface of the substrate to a depth of 300 nm is 7×10.sup.19/cm.sup.3 or less.

4. The method for manufacturing a semiconductor silicon wafer in claim 1, wherein the thickness of the thermal oxide film on the substrate surface is 20 nm or more and 150 nm or less in the heat treatment step in an oxidizing atmosphere.

Description

BRIEF DESCRIPTION OF DRAWINGS

[0053] FIG. 1 is a flowchart of an embodiment of a manufacturing method according to the present invention;

[0054] FIG. 2 shows the results of Experiment 1, illustrating a relationship between keeping time and the number of LPDs (65 nm);

[0055] FIGS. 3(a) and 3(b) show the results of Experiment 2, and FIG. 3(a) is a photograph of the backside of a silicon wafer substrate and FIG. 3(b) is a partially enlarged photograph of the photograph in FIG. 3(a);

[0056] FIG. 4 shows the results of Experiment 4, illustrating a relationship between the size of Si-P defects and the density of Si-P defects;

[0057] FIG. 5 shows the results of Experiment 5, illustrating the relationship of the density of phosphorus against the depth from the surface; and

[0058] FIG. 6 is a schematic structural diagram of a pulling-up apparatus provided with a water cooler.

DESCRIPTION OF EMBODIMENTS

[0059] Embodiments of a manufacturing method of semiconductor silicon wafers according to the present invention will be described based on FIGS. 1 and 2. The embodiment shown below is an example, and the present invention is not limited thereto.

[0060] The silicon wafer substrate used in a manufacturing method of semiconductor silicon wafers according to the present invention is a substrate sliced from a silicon single crystal ingot grown by the Czochralski method. The substrate is doped with phosphorus, is adjusted to have a resistivity of 1.05 mΩ.Math.cm or less, equivalent to a phosphorus concentration of 7×10.sup.19 atoms/cm.sup.3, and adjusted to have a solid-solution oxygen concentration of 0.9×10.sup.18/cm.sup.3, and contains Si-P defects. (Step S1)

[0061] The substrate is prepared by growing a silicon single crystal by the Czochralski method, when fabricating the silicon single crystal ingot, the temperature gradient is made large to inhibit a constitutional supercooling phenomenon and to inhibit the generation of P-aggregation defects (Si-P defects) by forcibly cooling the crystal with a water cooler installed inside the pulling-up furnace, pulling up at a pulling-up speed of 0.5 mm/min or more and 1.0 mm/min or less, and applying a magnetic field of 2000 G or more and 4000 G or less.

[0062] Specifically, for example, a pulling-up apparatus 1 shown in FIG. 6 can be used; in the pulling-up apparatus 1, a cylindrical water cooler 3 is installed between the upper part of the pulling-up furnace 2 and a shield plate 4, and the water cooler 3 cools the silicon single crystal 5 being pulled up forcibly. In the drawings, referential numeral 6 denotes a quartz glass crucible, referential numeral 7 denotes a heater, referential numeral 8 denotes a magnetic field application unit, and referential numeral 9 denotes a wire for pulling up a silicon single crystal.

[0063] Further, the substrate is preferably manufactured by slicing a silicon single crystal ingot such that the slicing angle against the primary plane orientation falls in a range of 0.1 degrees to 0.4 degrees. The slicing angle affects the growth and annihilation of SF at the deposition of an epitaxial layer. The principal plane orientation is Si (100), and the slicing angle against the primary plane orientation falls in a range of 0.1 degrees to 0.4 degrees.

[0064] Namely, by setting the slicing angle to be in a range of 0.1 degrees to 0.4 degrees against the principal plane orientation, a silicon step terrace is formed that would be a path for the movement of silicon atoms during epitaxial layer formation. By the formation of the step terraces, silicon atoms can move, strains of silicon atoms are eliminated, and SF defects are annihilated. Due to the formation of the silicon step terrace, silicon atoms can move along the terrace. The movement allows the removal of the strains of the silicon atoms and the elimination of the SF.

[0065] As described above, the manufactured silicon wafer substrates have a resistivity of 1.05 mΩ.Math.cm or less and the solid-solution oxygen concentration of 0.9×10.sup.18 atoms/cm.sup.3 or less and contain Si-P defects that are essentially defects formed by aggregation of phosphorus in the crystal (Step S1). Silicon wafer substrates demanded in the technical field have a resistivity of 1.05 mΩ.Math.cm or less, the solid-solution oxygen concentration of 0.9×10.sup.18 atoms/cm.sup.3 or less. Though Si-P defects are inhibited by the above-described method of silicon wafer substrates, Si-P defects still remain.

[0066] The above values of the resistivity and the solid-solution oxygen concentration can be achieved by adjusting the dopant concentration, the pulling-up speed, and the magnetic field intensity.

[0067] The Si-P defects of thus prepared silicon wafer substrates desirably have less than 100 nm in side length and the concentration of the defects less than 1×10.sup.12 /cm.sup.3.

[0068] When the maximum side length of the Si-P defects is 100 nm or more, Si-P defects reveal as SF (LPD) after the formation of the epitaxial layer. Also when the density of the Si-P defects is 1×10.sup.12 /cm.sup.3 or more, Si-P defects reveal as SF (LPD) after the step of deposition of an epitaxial layer.

[0069] Therefore, it is desirable that the maximum side length of the Si-P defects is less than 100 nm, the density of the Si-P defects is less than 1×10.sup.12 /cm.sup.3, and the crystal growth so adjusted is desirably performed.

[0070] Next, a silicon oxide film is formed on the back surface of the silicon wafer substrate (Step S2). For power MOSFET devices, a silicon oxide film is generally formed on the back surface of the wafer, and the silicon oxide film is formed by low-temperature CVD at a temperature less than 500° C., for example. The silicon oxide film is formed to a thickness of at least 300 nm only on the backside of the wafer. This silicon oxide film is for suppressing resistivity anomalies (auto-doping) in an epitaxially grown layer due to the phosphorus desorption from the backside of the wafer substrate when the silicon epitaxial layer is to be deposited thereafter.

[0071] The CVD oxide film, however, is generally low-density silicon dioxide, has micropores, contains much moisture, and has poor film quality.

[0072] However, when the silicon wafer substrate is heat-treated in an oxidizing atmosphere in the subsequent steps, oxygen gas penetrates the micropores and fills them by forming thermal oxide films, and densifies the CVD oxide film. Further, there is no risk of deterioration of the hazing on the substrate surface due to the formation of oxide film on the substrate surface even though moisture evaporates from the CVD oxide film.

[0073] Subsequently, the front surface of the wafer substrate is mirror-polished. (Step S3)

[0074] Mirror-polishing is carried out by pressing and rotating the wafer substrate surface to a polishing cloth with flowing a slurry containing silica particles. The reason why the mirror-polishing is performed in step S3 is also the removal of damages that are caused to the surface of the wafer by coming into contact with the protecting tape when the silicon oxide film is deposited on the backside of the wafer. The mirror-polishing does not decrease the Si-P defects.

[0075] Then, the wafer substrate is kept at a temperature of 1100° C. or higher and 1250° C. or lower for 30 minutes or longer and 120 minutes or shorter. (Step S4)

[0076] The atmosphere in the furnace for the heat treatment is an oxidizing atmosphere, or oxygen gas O.sub.2, specifically. Consequently, a thermal oxide film is formed on the surface of the wafer substrate by the heat treatment to a thickness of 20 nm or thicker and 150 nm or less. The thickness of the thermal oxide film is controlled by adjusting the partial pressure of the oxidizing gas of oxygen O.sub.2.

[0077] The Si-P defects are effectively annihilated by keeping the substrate at a temperature of 1100° C. or higher and 1250° C. or lower for 30 minutes or longer and 120 minutes or shorter. As a result, SF defects in the epitaxial layer are inhibited. It is not desirable to keep the substrate at less than 1100° C. or for less than 30 minutes because Si-P defects cannot be sufficiently annihilated, and keep the substrate at more than 1250° C. or for longer than 120 minutes because there may be a risk of introducing slip dislocations into the substrate.

[0078] When the thickness of the thermal oxide film is less than 20 nm, it is not desirable because the in-plane uniformity of the thermal oxide film is poor and gas etching occurs due to active oxidization in some parts of the silicon wafer substrate.

[0079] In contrast, when the thickness of the thermal oxide film is more than 150 nm, it is not desirable because the CVD oxide film on the backside of the substrate cannot leave 300 nm or more in the removal process of the front surface oxide film.

[0080] Next, the oxide film on the front surface of the substrate is completely removed by an acidic solution or acidic atmosphere. (Step S5)

[0081] By controlling the thermal oxide film thickness on the surface of the wafer substrate by the heat treatment described above to a thickness of 20 nm or thicker and 150 nm or less, by immersing the entire substrate in a dilute hydrofluoric solution with an HF concentration of 0.5%, for example, the thermal oxide film on the front surface of the substrate is completely removed but the CVD oxide film on the backside of the substrate remains 300 nm or more.

[0082] The process of removing the oxide film is desirably included because not only for the cleaning of the silicon surface but also for the annihilation of Si-P defects the removal of the surface natural oxide film is necessary.

[0083] In addition to immersing the entire substrate in a dilute hydrofluoric solution with an HF concentration of 0.5%, the surface natural oxide film may be removed by an acidic atmosphere such as hydrogen chloride HCl.

[0084] In addition, the surface cleaning treatment is performed on the substrate prior to the epitaxial layer deposition process. (Step S6) .

[0085] In the surface cleaning treatment step, silicon on the surface is etched by 50 nm or more to 150 nm or less by a mixed gas of hydrogen H.sub.2 and hydrogen chloride HCl.

[0086] SF after the epitaxial layer deposition can be further reduced by performing surface cleaning treatment. The defects removal by hydrogen chloride gas HCl is effective and a mixed gas of hydrogen H.sub.2 and hydrogen chloride HCl as a carrier is desirably employed.

[0087] The depth of the remaining defects is approximately 100 nm or less at the finish of step 4. Thus, the etching depth of surface silicon to 50 nm or more and 150 nm or less is appropriate if the productivity is considered.

[0088] Subsequently, a monocrystalline silicon epitaxial layer is deposited to a thickness of 1.3 .Math.m or more and 10.0 .Math.m or less. The silicon deposition temperature is 1100° C. or higher and 1150° C. or lower and the deposition rate is 3.5 .Math.m/min or more and 6.0 .Math.m/min or less. (Step S7)

[0089] As a result of studies, it is found that there is an appropriate combination of the growth rate and temperature for monocrystalline silicon epitaxial layer depoition for the reduction of SF. It is found that LPDs can be inhibited by setting the silicon deposition temperature to 1100° C. or higher and 1150° C. or lower and the deposition rate to 3.5 .Math.m/min or more and 6.0 .Math.m/min or less.

[0090] As an example specifically, a silicon wafer substrate was prepared by slicing a 200 mm diameter single crystal silicon ingot with the crystal orientation of (001) grown by the Czochralski method. An oxide film was formed on the backside of the silicon wafer substrate. The wafer substrate was mirror-polished and heat-treated in an oxidizing atmosphere. The removal of the oxide film on the front surface and the surface cleaning treatment was applied.

[0091] The single crystal doped with red phosphorus was pulled up at a pulling-up speed of 0.8 mm/min while applying a magnetic field of 3000 G. The wafer substrate has a resistivity of 0.80 mΩ.Math.cm and a concentration of oxygen of 0.8×10.sup.18 atoms/cm.sup.3, and the slicing angle is 0.3 degrees.

[0092] In addition, an oxide film was deposited on the backside of the substrate by CVD at 500° C. The front surface of the substrate was mirror-polished by mechanical polishing using silica slurry and a polishing cloth. Then the substrate was heat-treated in an oxygen O.sub.2 gas atmosphere and immersed in a diluted HF solution with a concentration of 0.5% to remove the thermal oxide film formed on the front side thoroughly. Further, an epitaxial layer was deposited to a thickness of 4 .Math.m in a mixed gas atmosphere of hydrogen H.sub.2 and silicon hydrogen chloride SiHCl.sub.3 at a deposition rate of 4 .Math.m/min at 1150° C.

[0093] Deposition of the silicon film is performed by the movement of silicon atoms on atomic steps on the surface. In this process, SF can be inhibited by correcting the disorder in the arrangement of silicon atoms originating from Si-P defects by the motion of silicon atoms. Therefore, to achieve both the silicon deposition and the correction, the condition of the deposition temperature to be 1100° C. or higher and 1150° C. and the deposition rate to be 3.5 .Math.m/min or more and 6.0 .Math.m/min or lower is necessary.

DESCRIPTION OF EMBODIMENTS

[0094] The present invention will be described further in detail based on Examples and Comparative Examples. The invention is not limited to the embodiments.

Experiment 1

[0095] Silicon wafer substrates with a diameter of 200 mm were used, which are doped with phosphorus (P) and have a resistivity adjusted to 1.05 mΩ.Math.cm or less and a concentration of solid-solution oxygen adjusted to 0.9×10.sup.18 atoms/cm.sup.3 or less.

[0096] An oxide film of 300 nm was deposited on the backside of the substrates by CVD at 500° C. The front surface of the substrates was mirror-polished by mechanical polishing using silica slurry and a polishing cloth.

[0097] Next, the substrates were heat-treated in an oxygen O.sub.2 gas atmosphere at temperatures of 1050° C., 1100° C., 1200° C., 1250° C., and 1270° C. kept for 15 minutes, 30 minutes, 120 minutes, and 180 minutes at each temperature, and immersed in a diluted HF solution with a concentration of 0.5 % to remove the thermal oxide film formed on the front side thoroughly. Further, an epitaxial layer was deposited to a thickness of 4 .Math.m in a mixed gas atmosphere of hydrogen H.sub.2 and silicon hydrogen chloride SiHCl.sub.3 at a deposition rate of 4 .Math.m/min at 1150° C.

[0098] After the deposition of the epitaxial layer, the number of LPDs of not less than 65 nm in size existing on the surface was measured with SP1 manufactured by KLA-Tencor Corporation. FIG. 2 shows the results.

[0099] As shown in FIG. 2, when processed at temperatures 1100° C. to 1270° C. and kept for 30 minutes to 120 minutes as a keeping time, the number of LPDs is equal to or less than 200 which is the criterion for judgment.

[0100] As shown in FIG. 2, for example, the graph lines at temperature 1270° C. and at temperature 1250° C. overlap each other, and above the temperature of 1250° C., the graph lines remained almost flat and unchanged.

Experiment 2

[0101] Verification of the thermal oxide films was conducted for the case the oxidizing atmosphere in Experiment 1 was changed to an Ar atmosphere.

[0102] The heat treatment condition is in an argon Ar atmosphere at 1200° C. for 120 minutes. As shown in FIGS. 3(a) and 3(b), for the case of the argon atmosphere, argon gas penetrates the micropores on the backside CVD film and etches the silicon substrate.

[0103] As a result, voids are formed, which is not preferable because voids may be a cause of particles adhering to the front surface side and auto doping of phosphorus, during the epitaxial layer deposition.

[0104] FIGS. 3(a) and 3(b) show the results of Experiment 2, and FIG. 3(a) is a photograph of the backside of a silicon wafer substrate and FIG. 3(b) is a partially enlarged photograph of the photograph in FIG. 3(a).

Experiment 3

[0105] The thickness of the backside oxide film that is necessary to prevent auto-doping during the epitaxial layer deposition was verified.

[0106] Specifically, silicon wafer substrates with a diameter of 200 mm were used, which are doped with phosphorus (P) and have a resistivity adjusted to 1.05 mΩ.Math.cm or less and a concentration of solid-solution oxygen adjusted equal to 0.9×10.sup.18 atoms/cm.sup.3 or less.

[0107] Next, backside oxide films were formed by the CVD method at 500° C., each having a thickness of 200 nm, 250 nm, 300 nm, 350 nm, and 400 nm.

[0108] Then, the front surface of the substrates was mirror-polished mechanically using silica slurry and a polishing cloth. Thereafter, heat treatment was conducted in an oxygen O.sub.2 atmosphere at a temperature of 1200° C. for 120 minutes. Further, the thermal oxide film formed on the front surface was completely removed by immersing in diluted hydrogen fluoride (HF) solution with a concentration of 0.5%. Then an epitaxial layer was deposited to a thickness of 4 .Math.m at a deposition rate of 4 .Math.m/min at 1150° C. in an atmosphere composed of hydrogen H.sub.2 and trichlorosilane SiHCl.sub.3.

[0109] Then the auto-doping of phosphorus into the epitaxial layer was examined by the measurement of spreading resistance analysis. Table 1 shows the results.

[0110] As shown in Table 1, it is found that the thickness of the backside oxide film of 300 nm or more can prevent the auto-doping of phosphorus into the epitaxial layer.

TABLE-US-00001 Residual Backside Oxide thickness (nm) Auto-doping of Phosphorus into Epitaxial layer 200 Yes 250 Yes 300 No 350 No 400 No

Experiment 4

[0111] Silicon crystals whose concentration of solid-solution oxygen is 0.9×10.sup.18 atoms/cm.sup.3 or less with the varied sizes of Si-P defects and density levels were prepared by varying the amount of doped phosphorus in the crystals from 7×10.sup.19 atoms/cm.sup.3 to 1.3×10.sup.20 atoms/cm.sup.3 and controlling the growth conditions.

[0112] The size and the density of the Si-P defects were measured by cross-sectional observation using a transmission electron microscope (TEM). FIG. 4 shows the results. The number of LPDs on the surface with a size of 65 nm or larger was inspected using SP-1 manufactured by KLA -Tencor. If the number of LPDs is equal to or less than 200, the result of the inspection is rated “Good” and if more than 200, it is rated “Not Good.”

[0113] As shown in FIG. 4, the case where the size of the SiP defects is less than 100 nm and the concentration is less than 1×10.sup.12 /cm.sup.3 gives the rating of “Good”. All the crystals rated “Good” have a phosphorus concentration of 7×10.sup.19 atoms/cm.sup.3 or less in common. That is, it is found that when the phosphorus concentration is 7×10.sup.19 atoms/cm.sup.3 or less, the size of Si-P defects is less than 100 nm and density thereof is less than 1×10.sup.12 /cm.sup.3 and the generation of Si-XP defects is inhibited.

Experiment 5

[0114] Silicon wafer substrates with a diameter of 200 mm were used, which are doped with phosphorus (P) of 1.3×10.sup.20 atoms/cm.sup.3 and have a resistivity of 0.6 mΩ.Math.cm and a concentration of solid-solution oxygen of 0.9×10.sup.18 atoms/cm.sup.3 or less, and a backside oxude film was formed by the CVD method to a thickness of 300 nm at 500° C.

[0115] Then, the front surface of the substrates was mirror-polished mechanically using silica slurry and a polishing cloth. Thereafter, heat treatment was conducted in an argon Ar or oxygen O.sub.2 atmosphere at 1200° C. for 120 minutes. Further, the thermal oxide film formed on the front surface was completely removed by immersing in diluted hydrogen fluoride (HF) solution with a concentration of 0.5%.

[0116] Then an epitaxial layer was deposited to a thickness of 4 .Math.m at a deposition rate of 4 .Math.m/min at 1150° C. in an atmosphere composed of hydrogen H.sub.2 and trichlorosilane SiHCl.sub.3.

[0117] As a result of the inspection of the number of LPDs on the surface with a size of 65 nm or larger using SP-1 manufactured by KLA-Tencor after the deposition of an epitaxial layer, the number of LPDs exceeds 200 for the case of heat treatment with argon Ar but is less than 200 for oxygen O.sub.2.

[0118] Regarding the reason for the difference in the number of LPDs after the epitaxial layer deposition between the oxygen case and the argon case, this depends on the profile of the concentration of phosphorus in the depth direction from the surface, as described below.

[0119] FIG. 5 is a result of the simulation of the concentration profile due to the heat treatment process. The boundary condition in the simulation is that the concentration of phosphorus at the substrate is 1.3×10.sup.20 atoms/cm.sup.3 and that at the uppermost surface is 1.0×10.sup.17 atoms/cm.sup.3. It is found that in the argon case, the concentration of phosphorus at 300 nm from the surface exceeds 7×10.sup.19 atoms/cm.sup.3, while in the case of O2, the concentration of phosphorus at a depth of 300 nm from the surface is 7×10.sup.19 atoms/cm.sup.3 or less due to the enhanced diffusion of phosphorus by the injection of interstitial silicon.

[0120] When the concentration of phosphorus is 7×10.sup.19atoms/cm.sup.3 or less, because the size of Si-P defects is less than 100 nm and the density thereof is less than 1×10.sup.12 /cm.sup.3, the number of LPDs is 200 or less, and thus the generation of Si-P defects is effectively inhibited.