The present invention discloses a composite gate dielectric layer for a Group III-V substrate and a method for manufacturing the same. The composite gate dielectric layer comprises: an Al.sub.xY.sub.2-xO.sub.3 interface passivation layer formed onthe group III-V substrate; and a high dielectric insulating layer formed on the Al.sub.xY.sub.2-xO.sub.3 interface passivation layer, wherein 1.2≦x≦1.9.The composite gate dielectric layer modifies the AI/Y ratio of the Al.sub.xY.sub.2-xO.sub.3 interface passivation layer, changes the average number of atomic coordination in the Al.sub.xY.sub.2-xO.sub.3 interface passivation layer, and decreases the interface state density and boundary trap density of the Group III-V substrate, increases the mobility of the MOS channel. By cooperation of the Al.sub.xY.sub.2-xO.sub.3 interface passivation layer and high dielectric insulation layer, it reduces leakage current and improvestolerance of the dielectric layer on the voltage, and improvesthe quality of the MOS capacitor of the Group III-V substrate and enhances its reliability.

A structure and formation method of a semiconductor device is provided. The semiconductor device structure includes an epitaxial structure over a semiconductor substrate. The semiconductor device structure also includes a dielectric fin over the semiconductor substrate. The dielectric fin extends upwards to exceed a bottom surface of the epitaxial structure. The dielectric fin has a dielectric structure and a protective shell, and the protective shell extends along sidewalls and a bottom of the dielectric structure. The protective shell has a first average grain size, and the dielectric structure has a second average grain size. The first average grain size is larger than the second average grain size.

The invention provides a process for forming crack-free dielectric films on a substrate. The process comprises the application of a dielectric precursor layer of a thickness from about 0.3 μm to about 1.0 μm to a substrate. The deposition is followed by low temperature heat pretreatment, prepyrolysis, pyrolysis and crystallization step for each layer. The deposition, heat pretreatment, prepyrolysis, pyrolysis and crystallization are repeated until the dielectric film forms an overall thickness of from about 1.5 μm to about 20.0 μm and providing a final crystallization treatment to form a thick dielectric film. The process provides a thick crack-free dielectric film on a substrate, the dielectric forming a dense thick crack-free dielectric having an overall dielectric thickness of from about 1.5 μm to about 20.0 μm.

Package-on-Package (PoP) structures and methods of forming the same are disclosed. In some embodiments, a method of forming a PoP structure may include: plating at least one through-assembly via (TAV) over a peripheral region of a conductive seed layer; forming a dam member over a central region of the conductive seed layer; and placing a die over the central region of the conductive seed layer. The dam member may be laterally separated from the die and disposed between the die and the at least one TAV. The method may further include encapsulating the die, the dam member, and the at least one TAV in a polymer material.

Films that can be useful in large area gap fill applications, such as in the formation of advanced 3D NAND devices, involve processing a semiconductor substrate by depositing on a patterned semiconductor substrate a doped silicon oxide film a doped silicon oxide film configured to expand upon annealing at a temperature above the films glass transition temperature, and annealing the doped silicon oxide film to a temperature above the film glass transition temperature. In some embodiments, reflow of the film may occur. The composition and processing conditions of the doped silicon oxide film may be tailored so that the film exhibits substantially zero as-deposited stress and substantially zero stress shift post-anneal.

A semiconductor device structure and a formation method are provided. The method includes forming a sacrificial base layer over a substrate and forming a semiconductor stack over the sacrificial base layer. The semiconductor stack has multiple sacrificial layers and multiple semiconductor layers laid out alternately. The method also includes forming a gate stack to partially cover the sacrificial base layer, the semiconductor layers, and the sacrificial layers. The method further includes removing the sacrificial base layer to form a recess between the substrate and the semiconductor stack. In addition, the method includes forming a metal-containing dielectric structure to partially or completely fill the recess. The metal-containing dielectric structure has multiple sub-layers.

Negative capacitance field-effect transistor (NCFET) and ferroelectric field-effect transistor (FE-FET) devices and methods of forming are provided. The gate dielectric stack of the NCFET and FE-FET devices includes a non-ferroelectric interfacial layer formed over the semiconductor channel, and a ferroelectric gate dielectric layer formed over the interfacial layer. The ferroelectric gate dielectric layer is formed by inserting dopant-source layers in between amorphous high-k dielectric layers and then converting the alternating sequence of dielectric layers to a ferroelectric gate dielectric layer by a post-deposition anneal (PDA). The ferroelectric gate dielectric layer has adjustable ferroelectric properties that may be varied by altering the precisely-controlled locations of the dopant-source layers using ALD/PEALD techniques. Accordingly, the methods described herein enable fabrication of stable NCFET and FE-FET FinFET devices that exhibit steep subthreshold slopes.

Negative capacitance field-effect transistor (NCFET) and ferroelectric field-effect transistor (FE-FET) devices and methods of forming are provided. The gate dielectric stack includes a ferroelectric gate dielectric layer. An amorphous high-k dielectric layer and a dopant-source layer are deposited sequentially followed by a post-deposition anneal (PDA). The PDA converts the amorphous high-k layer to a polycrystalline high-k film with crystalline grains stabilized by the dopants in a crystal phase in which the high-k dielectric is a ferroelectric high-k dielectric. After the PDA, the remnant dopant-source layer may be removed. A gate electrode is formed over remnant dopant-source layer (if present) and the polycrystalline high-k film.

[Object] To provide a FeFET and a method of its manufacture, the FeFET having a ferroelectric whose film thickness (dr) is made small and so nanofine as to range in: 59 nm<dr<150, without impairing the data retention property of not less than 10.sup.5 seconds and the data rewrite withstand property of not less than 10.sup.8 times, of those that have hitherto been developed, and the FeFET allowing data to be written with a writing voltage whose absolute value is not more than 3.3 volts.

[Means for Solving] In methods of making a device in which an insulator, a film made of constituent elements of a bismuth layered perovskite crystalline ferroelectric and a metal are sequentially formed in the indicated order on a semiconductor substrate and thereafter are annealed for ferroelectric crystallization, thereby preparing the device composed of the semiconductor, insulator, ferroelectric and metal, a method of making a semiconductor ferroelectric memory element in which the film is composed of Ca. Sr, Bi, Ta and oxygen atoms, the metal is Ir or Pt or an alloy of Ir and Pt, or Ru, and the annealing for ferroelectric crystallization is performed in a mixed gas having oxygen added to nitrogen or a mixed gas having oxygen added to argon.

An under layer film having excellent surface planarity is provided. In one aspect, the under layer film-forming composition for imprints includes a (meth)acrylic resin (A) containing an ethylenic unsaturated group (P) and a nonionic hydrophilic group (Q), and having a weight average molecular weight of 1,000 or larger; and a solvent (B), the resin (A) having an acid value of smaller than 1.0 mmol/g. In another aspect, the under layer film-forming composition for imprints includes a (meth)acrylic resin (A2) containing an ethylenic unsaturated group (P), and containing, as a nonionic hydrophilic group (Q), a cyclic substituent (Q2) having a carbonyl group in the cyclic structure thereof, with a weight average molecular weight of 1,000 or larger; and a solvent (B).