Patent classifications
H01L21/02422
Method for forming a glass substrate with a depleted surface layer and polycrystalline-silicon TFT built thereon
There is disclosed a method for chemically treating a display glass substrate by treating at least one surface of the glass substrate with a heated solution containing HCl to form a depletion layer at the surface and under the surface of the glass substrate. The disclosure also relates to display glass substrates containing the depletion layer made by the disclosed process. In addition, the disclosure relates to methods of making thin-film transistors (“TFTs”) on these display glass substrates by depositing a Si layer directly on the chemically treated surface of the glass substrate, and annealing the Si layer to form polycrystalline silicon.
Method of manufacturing compound film
An amount of nitrogen in a compound film is controlled. A method of manufacturing compound film comprising forming films laminated on a substrate placed at a film forming chamber is provided. According to the method of manufacturing compound film, a first compound layer including one or more elements selected from metal elements and semimetal elements and oxygen element and a second compound layer including one or more elements and nitrogen element are laminated alternately. The first compound layer is formed by a Filtered Arc Ion Plating method and the second compound layer is formed by a sputtering method.
Thin film transistor array panel and manufacturing method thereof
A thin film transistor array panel includes a substrate and a gate line disposed on the substrate. The gate line includes a gate electrode. A gate insulating layer is disposed on the gate line. An oxide semiconductor layer is disposed on the gate insulating layer. The oxide semiconductor layer at least partially overlaps the gate electrode. A data line is disposed on the oxide semiconductor layer. The data line includes a source electrode and a drain electrode facing the source electrode. The oxide semiconductor layer includes tungsten, indium, zinc, or tin.
Metal-induced crystallization of amorphous silicon in an oxidizing atmosphere
Techniques are provided for forming thin film transistors having a polycrystalline silicon active layer formed by metal-induced crystallization (MIC) of amorphous silicon in an oxidizing atmosphere. In an aspect, a transistor device, is provided that includes a source region and a drain region formed on a substrate, and an active channel region formed on the substrate and electrically connecting the source region and the drain region. The active channel region is formed with a polycrystalline silicon layer having resulted from annealing an amorphous silicon layer formed on the substrate and having a metal layer formed thereon, wherein the annealing of the amorphous silicon layer was at least partially performed in an oxidizing ambience, thereby resulting in crystallization of the amorphous silicon layer to form the polycrystalline silicon layer.
Method of growing III-V semiconductor films for tandem solar cells
A method of growing a III-V semiconductor compound film for a semiconductor device including the steps of depositing a textured oxide buffer layer on an inexpensive substrate, depositing a metal-inorganic film from a eutectic alloy on the buffer layer, the metal being a component of a III-V compound and forming a layer on the inorganic film on which additional elements from the III-V compound are added, forming a top layer of a tandem solar cell.
METHOD OF FORMING TIN OXIDE LAYER USING TIN METAL TARGET
Provided is a method of forming a tin oxide layer using a tin metal target which forms the tin oxide layer on a glass substrate using the tin metal target. The present invention provides the method of forming a tin oxide layer using a tin metal target, which includes forming a tin oxide buffer layer (SnO.sub.2) on the glass substrate by sputtering using the tin metal target and forming a tin oxide (SnO.sub.2−x) semiconductor layer (0<x≦0.01) on the tin oxide buffer layer by sputtering using the tin metal target.
MINIATURIZED ELECTRONIC COMPONENT WITH REDUCED RISK OF BREAKAGE AND METHOD FOR PRODUCING SAME
A method for producing miniaturized electronic components is provided, where the miniaturized electronic components are obtained as singularized parts of a sheet-like glass which has structures applied thereon, in particular at least one layer. The method includes the steps of: providing a sheet-like glass toughened at least during a time period, as a substrate material; applying structures onto the substrate, in particular in the form of a sequence of coating processes and by processes for patterning of layers, so that at least portions of the substrate carry structures while other portions of the substrate remain free; subjecting the substrate carrying the structures to a thermal load; and singularizing so that the portions of the substrate carrying structures are obtained in singularized form. A miniaturized electronic component produced in this manner is also provided.
Semiconductor device
A transistor includes a multilayer film in which an oxide semiconductor film and an oxide film are stacked, a gate electrode, and a gate insulating film. The multilayer film overlaps with the gate electrode with the gate insulating film interposed therebetween. The multilayer film has a shape having a first angle between a bottom surface of the oxide semiconductor film and a side surface of the oxide semiconductor film and a second angle between a bottom surface of the oxide film and a side surface of the oxide film. The first angle is acute and smaller than the second angle. Further, a semiconductor device including such a transistor is manufactured.
Sputtering target
A sputtering target including a sintered body: the sintered body including: indium oxide doped with Ga or indium oxide doped with Al, and a positive tetravalent metal in an amount of exceeding 100 at. ppm and 1100 at. ppm or less relative to the total of Ga and indium, or Al and indium, the crystal structure of the sintered body substantially including a bixbyite structure of indium oxide.
Structures having isolated graphene layers with a reduced dimension
Graphite-based devices with a reduced characteristic dimension and methods for forming such devices are provided. One or more thin films are deposited onto a substrate and undesired portions of the deposited thin film or thin films are removed to produce processed elements with reduced characteristic dimensions. Graphene layers are generated on selected processed elements or exposed portions of the substrate after removal of the processed elements. Multiple sets of graphene layers can be generated, each with a different physical characteristic, thereby producing a graphite-based device with multiple functionalities in the same device.